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# FPGA天气播报
## ①uart协议
## ②JQ8400
## ③ESP8266

@ -0,0 +1,32 @@
module key_filter
(
input wire sys_clk , //50MHZ
input wire sys_rst_n , //
input wire key_in , //
output reg key_flag //
);
parameter CNT_20MS_MAX = 20'd1_000_000 ; //20ms
reg [19:0] cnt_20ms ; //20ms
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_20ms <= 20'b0;
else if(key_in == 1'b1)
cnt_20ms <= 20'b0;
else if((cnt_20ms >= CNT_20MS_MAX - 1'b1)&&(key_in == 1'b0))
cnt_20ms <= CNT_20MS_MAX;
else
cnt_20ms <= cnt_20ms + 1'b1;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
key_flag <= 1'b0;
else if(cnt_20ms == CNT_20MS_MAX - 1'b1)
key_flag <= 1'b1;
else
key_flag <= 1'b0;
endmodule

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module uart_rx
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 //
)
(
input wire sys_clk , //50MHZ
input wire sys_rst_n , //
input wire rx , //线
output reg [7:0] po_data , //8
output reg po_flag //
);
localparam CNT_BAUD_MID = CLK_FRE / (BAUD_RATE*2) , //
CNT_BAUD_MAX = CLK_FRE / BAUD_RATE ; //
reg rx_d0 ; //FPGA
reg rx_d1 ; //FPGA
reg rx_d2 ; //FPGA
reg work_valid ; //FPGA
reg [14:0] cnt_baud ; //
reg [3:0] cnt_bit ; //
reg flag_bit ; //
reg [7:0] po_data_reg ; //
wire start_en ; //
wire stop_en ; //
assign start_en = ((rx_d1 == 1'b0)&&(rx_d2 == 1'b1)) ? 1'b1 : 1'b0 ;
assign stop_en = ((cnt_baud == CNT_BAUD_MID - 1'b1)&&(cnt_bit == 4'd8)) ? 1'b1 : 1'b0 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
begin
rx_d0 <= 1'b0 ;
rx_d1 <= 1'b0 ;
rx_d2 <= 1'b0 ;
end
else
begin
rx_d0 <= rx ;
rx_d1 <= rx_d0 ;
rx_d2 <= rx_d1 ;
end
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
work_valid <= 1'b0 ;
else if(start_en == 1'b1)
work_valid <= 1'b1 ;
else if(stop_en == 1'b1)
work_valid <= 1'b0 ;
else
work_valid <= work_valid ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_baud <= 15'd0 ;
else if((cnt_baud == CNT_BAUD_MAX - 1'b1)&&(work_valid == 1'b1))
cnt_baud <= 15'd0 ;
else if(work_valid == 1'b1)
cnt_baud <= cnt_baud + 1'b1 ;
else
cnt_baud <= 15'd0 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_bit <= 4'd0 ;
else if((cnt_baud == CNT_BAUD_MAX - 1'b1)&&(work_valid == 1'b1)&&(cnt_bit == 4'd8))
cnt_bit <= 4'd0 ;
else if((cnt_baud == CNT_BAUD_MAX - 1'b1)&&(work_valid == 1'b1))
cnt_bit <= cnt_bit + 1'b1 ;
else if(work_valid == 1'b0)
cnt_bit <= 4'd0 ;
else
cnt_bit <= cnt_bit ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
flag_bit <= 1'b0 ;
else if((cnt_baud == CNT_BAUD_MID - 2'd3)&&(cnt_bit != 4'd0))
flag_bit <= 1'b1 ;
else
flag_bit <= 1'b0 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
po_data_reg <= 8'd0 ;
else if((flag_bit == 1'b1)&&(work_valid == 1'b1))
po_data_reg <= {rx_d2,po_data_reg[7:1]} ;
else if(work_valid == 1'b0)
po_data_reg <= 8'd0 ;
else
po_data_reg <= po_data_reg ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
po_data <= 8'd0 ;
else if((cnt_bit == 4'd8)&&(stop_en == 1'b1))
po_data <= po_data_reg ;
else
po_data <= po_data ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
po_flag <= 1'b0 ;
else if((cnt_bit == 4'd8)&&(stop_en == 1'b1))
po_flag <= 1'b1 ;
else
po_flag <= 1'b0 ;
endmodule

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module uart_tx
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 //
)
(
input wire sys_clk , //50MHZ
input wire sys_rst_n , //
input wire [7:0] pi_data , //8bit
input wire pi_flag , //
output reg tx //线
);
localparam CNT_BAUD_MAX = CLK_FRE / BAUD_RATE ; //
reg work_en ; //FPGA
reg [14:0] cnt_baud ; //
reg [3:0] cnt_bit ; //
wire stop_en ; //
assign stop_en = ((cnt_bit == 4'd8)&&(cnt_baud == CNT_BAUD_MAX - 1'b1))? 1'b1 : 1'b0 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
work_en <= 1'b0 ;
else if(pi_flag == 1'b1)
work_en <= 1'b1 ;
else if(stop_en == 1'b1)
work_en <= 1'b0 ;
else
work_en <= work_en ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_baud <= 15'd0 ;
else if((work_en == 1'b1)&&(cnt_baud == CNT_BAUD_MAX - 1'b1))
cnt_baud <= 15'd0 ;
else if(work_en == 1'b1)
cnt_baud <= cnt_baud + 1'b1 ;
else
cnt_baud <= 15'd0 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_bit <= 4'd0 ;
else if((cnt_bit == 4'd8)&&(stop_en == 1'b1)&&(work_en == 1'b1))
cnt_bit <= 4'd0 ;
else if((work_en == 1'b1)&&(cnt_baud == CNT_BAUD_MAX - 1'b1))
cnt_bit <= cnt_bit + 1'b1 ;
else if(work_en == 1'b0)
cnt_bit <= 4'd0 ;
else
cnt_bit <= cnt_bit ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
tx <= 1'b1 ;
else if((cnt_bit == 4'd0)&&(pi_flag == 1'b1))
tx <= 1'b0 ;
else if(work_en == 1'b1)
case(cnt_bit)
4'd0 : tx <= 1'b0 ;
4'd1 : tx <= pi_data[0] ;
4'd2 : tx <= pi_data[1] ;
4'd3 : tx <= pi_data[2] ;
4'd4 : tx <= pi_data[3] ;
4'd5 : tx <= pi_data[4] ;
4'd6 : tx <= pi_data[5] ;
4'd7 : tx <= pi_data[6] ;
4'd8 : tx <= pi_data[7] ;
default : tx <= 1'b1 ;
endcase
else
tx <= 1'b1 ;
endmodule

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module jq8400_ctrl
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire key_flag ,
input wire [39:0] wifi_data , //[39:32] sign; [31:16] wthr_data; [15:0] tem_data;
output wire rx_jq8400
);
parameter CLK_FRE = 'd50_000_000 ,
BAUD_RATE = 'd9600 ;
parameter CNT_WAIT_MAX= (CLK_FRE/BAUD_RATE + 'd100) * 10 ;
parameter IDLE = 1'd0 ,
DATA_CTRL = 1'd1 ;
parameter INSTR_NUM = 4'd15 ;
wire [119:0] instr_data_reg[45:0] ;
reg [119:0] instr_data ;
reg [3:0] cnt_instr ; //9
reg [3:0] cnt_num ; //
reg [7:0] tx_data ; //
reg tx_flag ; //
reg [26:0] cnt_wait ; //
reg [26:0] cnt_wait_max; //
reg skip_en ; //
reg n_state ; //
reg c_state ; //
// reg inf_flag_d ; //
// wire inf_raise ; //沿
// assign inf_raise = inf_flag & (~inf_flag_d) ;
// always@(posedge sys_clk or negedge sys_rst_n)
// if(sys_rst_n == 1'b0)
// inf_flag_d <= 1'b0 ;
// else
// inf_flag_d <= inf_flag ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
c_state <= IDLE ;
else
c_state <= n_state ;
always@(*)
case(c_state)
IDLE : if(skip_en == 1'b1)
n_state = DATA_CTRL ;
else
n_state = IDLE ;
DATA_CTRL : if(skip_en == 1'b1)
n_state = IDLE ;
else
n_state = DATA_CTRL ;
default : n_state = IDLE ;
endcase
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
begin
cnt_wait <= 27'd0 ;
cnt_num <= 4'd0 ;
cnt_instr <= 4'd0 ;
skip_en <= 1'b0 ;
tx_data <= 8'd0 ;
tx_flag <= 1'b0 ;
end
else
case(c_state)
IDLE :begin
if((cnt_instr == 4'd0)&&(key_flag == 1'b1))
skip_en <= 1'b1 ;
else if((cnt_wait == cnt_wait_max - 2'd2)&&(cnt_instr > 4'd0))
skip_en <= 1'b1 ;
else
skip_en <= 1'b0 ;
if((cnt_wait == cnt_wait_max - 1'b1)||(skip_en == 1'b1))
cnt_wait <= 27'd0 ;
else
cnt_wait <= cnt_wait + 1'b1 ;
end
DATA_CTRL :begin
if(cnt_wait == CNT_WAIT_MAX - 1'b1)
cnt_wait <= 27'd0 ;
else
cnt_wait <= cnt_wait + 1'b1 ;
if((cnt_wait == CNT_WAIT_MAX - 1'b1)&&(cnt_num == INSTR_NUM - 1'b1))
cnt_num <= 4'd0 ;
else if(cnt_wait == CNT_WAIT_MAX - 1'b1)
cnt_num <= cnt_num + 1'b1 ;
else
cnt_num <= cnt_num ;
if((cnt_instr == 4'd8)&&(cnt_wait == CNT_WAIT_MAX - 1'b1)&&(cnt_num == INSTR_NUM - 1'b1))
cnt_instr <= 4'd0 ;
else if((cnt_wait == CNT_WAIT_MAX - 1'b1)&&(cnt_num == INSTR_NUM - 1'b1))
cnt_instr <= cnt_instr + 1'b1 ;
else
cnt_instr <= cnt_instr ;
if((cnt_wait == CNT_WAIT_MAX - 2'd2)&&(cnt_num == INSTR_NUM - 1'b1))
skip_en <= 1'b1 ;
else
skip_en <= 1'b0 ;
if(cnt_wait == 27'd0)
tx_flag <= 1'b1 ;
else
tx_flag <= 1'b0 ;
case(cnt_num)
4'd14 : tx_data <= instr_data[007:000] ;
4'd13 : tx_data <= instr_data[015:008] ;
4'd12 : tx_data <= instr_data[023:016] ;
4'd11 : tx_data <= instr_data[031:024] ;
4'd10 : tx_data <= instr_data[039:032] ;
4'd09 : tx_data <= instr_data[047:040] ;
4'd08 : tx_data <= instr_data[055:048] ;
4'd07 : tx_data <= instr_data[063:056] ;
4'd06 : tx_data <= instr_data[071:064] ;
4'd05 : tx_data <= instr_data[079:072] ;
4'd04 : tx_data <= instr_data[087:080] ;
4'd03 : tx_data <= instr_data[095:088] ;
4'd02 : tx_data <= instr_data[103:096] ;
4'd01 : tx_data <= instr_data[111:104] ;
4'd00 : tx_data <= instr_data[119:112] ;
default : tx_data <= 8'd0 ;
endcase
end
default :begin
cnt_wait <= 27'd0 ;
cnt_num <= 4'd0 ;
cnt_instr <= 4'd0 ;
skip_en <= 1'b0 ;
tx_data <= 8'd0 ;
tx_flag <= 1'b0 ;
end
endcase
always@(*)
case(cnt_instr)
4'd0 : cnt_wait_max = 27'd0 ;
4'd1 : cnt_wait_max = 27'd100_000_000 ;
4'd2 : cnt_wait_max = 27'd50_000_000 ;
4'd3 : cnt_wait_max = 27'd50_000_000 ;
4'd4 : cnt_wait_max = 27'd50_000_000 ;
4'd5 : cnt_wait_max = 27'd50_000_000 ;
4'd6 : cnt_wait_max = 27'd50_000_000 ;
4'd7 : cnt_wait_max = 27'd50_000_000 ;
4'd8 : cnt_wait_max = 27'd100_000_000 ;
default : cnt_wait_max = 27'd0 ;
endcase
always@(*)
case(cnt_instr)
4'd0 : instr_data = instr_data_reg[00] ;
4'd1 : case(wifi_data[31:16])
16'h30_30 : instr_data = instr_data_reg[01] ;
16'h30_31 : instr_data = instr_data_reg[02] ;
16'h30_32 : instr_data = instr_data_reg[03] ;
16'h30_33 : instr_data = instr_data_reg[04] ;
16'h30_34 : instr_data = instr_data_reg[05] ;
16'h30_35 : instr_data = instr_data_reg[06] ;
16'h30_36 : instr_data = instr_data_reg[07] ;
16'h30_37 : instr_data = instr_data_reg[08] ;
16'h30_38 : instr_data = instr_data_reg[09] ;
16'h30_39 : instr_data = instr_data_reg[10] ;
16'h31_30 : instr_data = instr_data_reg[11] ;
16'h31_31 : instr_data = instr_data_reg[12] ;
16'h31_32 : instr_data = instr_data_reg[13] ;
16'h31_33 : instr_data = instr_data_reg[14] ;
16'h31_34 : instr_data = instr_data_reg[15] ;
16'h31_35 : instr_data = instr_data_reg[16] ;
default : instr_data = 120'd0 ;
endcase
4'd2 : instr_data = instr_data_reg[17] ;
4'd3 : if(wifi_data[39:32] == 8'h30)
instr_data = instr_data_reg[18] ;
else
instr_data = 120'd0 ;
4'd4 : case(wifi_data[15:8])
8'h30 : instr_data = 120'd0 ;
8'h31 : instr_data = instr_data_reg[19] ;
8'h32 : instr_data = instr_data_reg[20] ;
8'h33 : instr_data = instr_data_reg[21] ;
8'h34 : instr_data = instr_data_reg[22] ;
8'h35 : instr_data = instr_data_reg[23] ;
8'h36 : instr_data = instr_data_reg[24] ;
8'h37 : instr_data = instr_data_reg[25] ;
8'h38 : instr_data = instr_data_reg[26] ;
8'h39 : instr_data = instr_data_reg[27] ;
default : instr_data = 120'd0 ;
endcase
4'd5 : if(wifi_data[15:8] > 8'h30)
instr_data = instr_data_reg[28] ;
else
instr_data = 120'd0 ;
4'd6 : case(wifi_data[7:0])
8'h30 : instr_data = 120'd0 ;
8'h31 : instr_data = instr_data_reg[19] ;
8'h32 : instr_data = instr_data_reg[20] ;
8'h33 : instr_data = instr_data_reg[21] ;
8'h34 : instr_data = instr_data_reg[22] ;
8'h35 : instr_data = instr_data_reg[23] ;
8'h36 : instr_data = instr_data_reg[24] ;
8'h37 : instr_data = instr_data_reg[25] ;
8'h38 : instr_data = instr_data_reg[26] ;
8'h39 : instr_data = instr_data_reg[27] ;
default : instr_data = 120'd0 ;
endcase
4'd7 : instr_data = instr_data_reg[29] ;
4'd8 : case(wifi_data[31:16])
16'h30_30 : instr_data = instr_data_reg[30] ;
16'h30_31 : instr_data = instr_data_reg[31] ;
16'h30_32 : instr_data = instr_data_reg[32] ;
16'h30_33 : instr_data = instr_data_reg[33] ;
16'h30_34 : instr_data = instr_data_reg[34] ;
16'h30_35 : instr_data = instr_data_reg[35] ;
16'h30_36 : instr_data = instr_data_reg[36] ;
16'h30_37 : instr_data = instr_data_reg[37] ;
16'h30_38 : instr_data = instr_data_reg[38] ;
16'h30_39 : instr_data = instr_data_reg[39] ;
16'h31_30 : instr_data = instr_data_reg[40] ;
16'h31_31 : instr_data = instr_data_reg[41] ;
16'h31_32 : instr_data = instr_data_reg[42] ;
16'h31_33 : instr_data = instr_data_reg[43] ;
16'h31_34 : instr_data = instr_data_reg[44] ;
16'h31_35 : instr_data = instr_data_reg[45] ;
default : instr_data = 120'd0 ;
endcase
default : instr_data = 120'd0 ;
endcase
//0
assign instr_data_reg[00] = 120'hAA_08_0B_02_2F_30_2A_2F_30_30_2A_3F_3F_3F_BE ; //
//1
assign instr_data_reg[01] = 120'hAA_08_0B_02_2F_31_2A_2F_30_30_2A_3F_3F_3F_BF ; //
assign instr_data_reg[02] = 120'hAA_08_0B_02_2F_31_2A_2F_30_31_2A_3F_3F_3F_C0 ; //
assign instr_data_reg[03] = 120'hAA_08_0B_02_2F_31_2A_2F_30_32_2A_3F_3F_3F_C1 ; //
assign instr_data_reg[04] = 120'hAA_08_0B_02_2F_31_2A_2F_30_33_2A_3F_3F_3F_C2 ; //
assign instr_data_reg[05] = 120'hAA_08_0B_02_2F_31_2A_2F_30_34_2A_3F_3F_3F_C3 ; //
assign instr_data_reg[06] = 120'hAA_08_0B_02_2F_31_2A_2F_30_35_2A_3F_3F_3F_C4 ; //
assign instr_data_reg[07] = 120'hAA_08_0B_02_2F_31_2A_2F_30_36_2A_3F_3F_3F_C5 ; //
assign instr_data_reg[08] = 120'hAA_08_0B_02_2F_31_2A_2F_30_37_2A_3F_3F_3F_C6 ; //
assign instr_data_reg[09] = 120'hAA_08_0B_02_2F_31_2A_2F_30_38_2A_3F_3F_3F_C7 ; //
assign instr_data_reg[10] = 120'hAA_08_0B_02_2F_31_2A_2F_30_39_2A_3F_3F_3F_C8 ; //
assign instr_data_reg[11] = 120'hAA_08_0B_02_2F_31_2A_2F_31_31_2A_3F_3F_3F_C1 ; //
assign instr_data_reg[12] = 120'hAA_08_0B_02_2F_31_2A_2F_31_30_2A_3F_3F_3F_C0 ; //
assign instr_data_reg[13] = 120'hAA_08_0B_02_2F_31_2A_2F_31_32_2A_3F_3F_3F_C2 ; //
assign instr_data_reg[14] = 120'hAA_08_0B_02_2F_31_2A_2F_31_33_2A_3F_3F_3F_C3 ; //
assign instr_data_reg[15] = 120'hAA_08_0B_02_2F_31_2A_2F_31_34_2A_3F_3F_3F_C4 ; //
assign instr_data_reg[16] = 120'hAA_08_0B_02_2F_31_2A_2F_31_35_2A_3F_3F_3F_C5 ; //
//2
assign instr_data_reg[17] = 120'hAA_08_0B_02_2F_32_2A_2F_30_30_2A_3F_3F_3F_C0 ; //
//3
assign instr_data_reg[18] = 120'hAA_08_0B_02_2F_33_2A_2F_30_30_2A_3F_3F_3F_C1 ; //
//4
assign instr_data_reg[19] = 120'hAA_08_0B_02_2F_34_2A_2F_30_31_2A_3F_3F_3F_C3 ; //
assign instr_data_reg[20] = 120'hAA_08_0B_02_2F_34_2A_2F_30_32_2A_3F_3F_3F_C4 ; //
assign instr_data_reg[21] = 120'hAA_08_0B_02_2F_34_2A_2F_30_33_2A_3F_3F_3F_C5 ; //
assign instr_data_reg[22] = 120'hAA_08_0B_02_2F_34_2A_2F_30_34_2A_3F_3F_3F_C6 ; //
assign instr_data_reg[23] = 120'hAA_08_0B_02_2F_34_2A_2F_30_35_2A_3F_3F_3F_C7 ; //
assign instr_data_reg[24] = 120'hAA_08_0B_02_2F_34_2A_2F_30_36_2A_3F_3F_3F_C8 ; //
assign instr_data_reg[25] = 120'hAA_08_0B_02_2F_34_2A_2F_30_37_2A_3F_3F_3F_C9 ; //
assign instr_data_reg[26] = 120'hAA_08_0B_02_2F_34_2A_2F_30_38_2A_3F_3F_3F_CA ; //
assign instr_data_reg[27] = 120'hAA_08_0B_02_2F_34_2A_2F_30_39_2A_3F_3F_3F_CB ; //
assign instr_data_reg[28] = 120'hAA_08_0B_02_2F_34_2A_2F_31_30_2A_3F_3F_3F_C3 ; //
//5
assign instr_data_reg[29] = 120'hAA_08_0B_02_2F_35_2A_2F_30_30_2A_3F_3F_3F_C3 ; //
//6
assign instr_data_reg[30] = 120'hAA_08_0B_02_2F_36_2A_2F_30_30_2A_3F_3F_3F_C4 ; //
assign instr_data_reg[31] = 120'hAA_08_0B_02_2F_36_2A_2F_30_31_2A_3F_3F_3F_C5 ; //
assign instr_data_reg[32] = 120'hAA_08_0B_02_2F_36_2A_2F_30_32_2A_3F_3F_3F_C6 ; //
assign instr_data_reg[33] = 120'hAA_08_0B_02_2F_36_2A_2F_30_33_2A_3F_3F_3F_C7 ; //
assign instr_data_reg[34] = 120'hAA_08_0B_02_2F_36_2A_2F_30_34_2A_3F_3F_3F_C8 ; //
assign instr_data_reg[35] = 120'hAA_08_0B_02_2F_36_2A_2F_30_35_2A_3F_3F_3F_C9 ; //
assign instr_data_reg[36] = 120'hAA_08_0B_02_2F_36_2A_2F_30_36_2A_3F_3F_3F_CA ; //
assign instr_data_reg[37] = 120'hAA_08_0B_02_2F_36_2A_2F_30_37_2A_3F_3F_3F_CB ; //
assign instr_data_reg[38] = 120'hAA_08_0B_02_2F_36_2A_2F_30_38_2A_3F_3F_3F_CC ; //
assign instr_data_reg[39] = 120'hAA_08_0B_02_2F_36_2A_2F_30_39_2A_3F_3F_3F_CD ; //
assign instr_data_reg[40] = 120'hAA_08_0B_02_2F_36_2A_2F_31_30_2A_3F_3F_3F_C5 ; //
assign instr_data_reg[41] = 120'hAA_08_0B_02_2F_36_2A_2F_31_31_2A_3F_3F_3F_C6 ; //
assign instr_data_reg[42] = 120'hAA_08_0B_02_2F_36_2A_2F_31_32_2A_3F_3F_3F_C7 ; //
assign instr_data_reg[43] = 120'hAA_08_0B_02_2F_36_2A_2F_31_33_2A_3F_3F_3F_C8 ; //
assign instr_data_reg[44] = 120'hAA_08_0B_02_2F_36_2A_2F_31_34_2A_3F_3F_3F_C9 ; //
assign instr_data_reg[45] = 120'hAA_08_0B_02_2F_36_2A_2F_31_35_2A_3F_3F_3F_CA ; //
uart_tx
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE )
)
uart_tx_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.pi_data (tx_data ),
.pi_flag (tx_flag ),
.tx (rx_jq8400 )
);
endmodule

@ -0,0 +1,83 @@
module weather_bcst
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 , //
INSTR_0 = "+++" , //退
INSTR_1 = "AT+SAVETRANSLINK=0" , //
INSTR_2 = "AT+CWMODE=1" , //wifi
INSTR_3 = "AT+RST" , //
INSTR_4 = "AT+CWJAP=\"FPGA\",\"12345678\"" , //wifiwifiFPGA12345678
INSTR_5 = "AT+CIFSR" , //IP
INSTR_6 = "AT+CIPSTART=\"TCP\",\"192.168.137.1\",8888" , //TCPIP192.168.135.1078888
INSTR_7 = "AT+CIPMODE=1" , //
INSTR_8 = "AT+CIPSEND" , //
ACK_OK = "OK" , //OK
ACK_ADD = "++" , //退
ACK_END = 16'h0d0a //_+
)
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire key_in ,
input wire tx_device ,
output wire rx_jq8400 ,
output wire rx_device ,
output wire [3:0] led_out ,
output wire [4:0] sel ,
output wire [7:0] dig ,
output wire test_rx
);
wire key_flag ;
wire [39:0] wifi_data ;
key_filter key_filter_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.key_in (key_in ),
.key_flag (key_flag )
);
weather_show
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE ),
.INSTR_0 (INSTR_0 ),
.INSTR_1 (INSTR_1 ),
.INSTR_2 (INSTR_2 ),
.INSTR_3 (INSTR_3 ),
.INSTR_4 (INSTR_4 ),
.INSTR_5 (INSTR_5 ),
.INSTR_6 (INSTR_6 ),
.INSTR_7 (INSTR_7 ),
.INSTR_8 (INSTR_8 ),
.ACK_OK (ACK_OK ),
.ACK_ADD (ACK_ADD ),
.ACK_END (ACK_END )
)
weather_show_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.tx_device (tx_device ),
.rx_device (rx_device ),
.sel (sel ),
.dig (dig ),
.wifi_data (wifi_data ),
.led_out (led_out ),
.test_rx (test_rx )
);
jq8400_ctrl jq8400_ctrl_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.key_flag (key_flag ),
.wifi_data (wifi_data ),
.rx_jq8400 (rx_jq8400 )
);
endmodule

@ -0,0 +1,160 @@
module ascii_trans
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 //
)
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire tx_device ,
input wire cfg_done ,
output reg [39:0] seg_data ,
output reg [39:0] wifi_data //wifi()
);
wire flag ;
wire [7:0] data ;
reg [7:0] unit ;
reg [7:0] ten ;
reg [7:0] hun ;
reg [7:0] tho ;
reg [7:0] t_tho ;
reg [2:0] cnt_flag ;
reg flag_d ;
(*noprune*)reg [9:0] cnt ;
// assign seg_data = ((flag_d == 1'b1)&&(cnt_flag == 3'd0)&&({t_tho,tho,hun,ten,unit} != seg_data)) ? {t_tho,tho,hun,ten,unit} : seg_data ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt <= 10'd0 ;
else if(flag == 1'b1)
cnt <= cnt + 1'b1 ;
else
cnt <= cnt ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
seg_data <= 40'hff_ffff_ffff ;
else if((flag_d == 1'b1)&&(cnt_flag == 3'd0)&&({t_tho,tho,hun,ten,unit} != seg_data))
seg_data <= {t_tho,tho,hun,ten,unit} ;
else
seg_data <= seg_data ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
flag_d <= 1'b0 ;
else
flag_d <= flag ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_flag <= 3'd0 ;
else if((cnt_flag == 3'd4)&&(flag == 1'b1)&&(cfg_done == 1'b1))
cnt_flag <= 3'd0 ;
else if((flag == 1'b1)&&(cfg_done == 1'b1))
cnt_flag <= cnt_flag + 1'b1 ;
else if(cfg_done == 1'b0)
cnt_flag <= 3'd0 ;
else
cnt_flag <= cnt_flag ;
always@(*)
case(wifi_data[7:0])
8'h30 : unit = 8'd0 ;
8'h31 : unit = 8'd1 ;
8'h32 : unit = 8'd2 ;
8'h33 : unit = 8'd3 ;
8'h34 : unit = 8'd4 ;
8'h35 : unit = 8'd5 ;
8'h36 : unit = 8'd6 ;
8'h37 : unit = 8'd7 ;
8'h38 : unit = 8'd8 ;
8'h39 : unit = 8'd9 ;
default : unit = 8'd0 ;
endcase
always@(*)
case(wifi_data[15:8])
8'h30 : ten = 8'd0 ;
8'h31 : ten = 8'd1 ;
8'h32 : ten = 8'd2 ;
8'h33 : ten = 8'd3 ;
8'h34 : ten = 8'd4 ;
8'h35 : ten = 8'd5 ;
8'h36 : ten = 8'd6 ;
8'h37 : ten = 8'd7 ;
8'h38 : ten = 8'd8 ;
8'h39 : ten = 8'd9 ;
default : ten = 8'd0 ;
endcase
always@(*)
case(wifi_data[23:16])
8'h30 : hun = 8'd0 ;
8'h31 : hun = 8'd1 ;
8'h32 : hun = 8'd2 ;
8'h33 : hun = 8'd3 ;
8'h34 : hun = 8'd4 ;
8'h35 : hun = 8'd5 ;
8'h36 : hun = 8'd6 ;
8'h37 : hun = 8'd7 ;
8'h38 : hun = 8'd8 ;
8'h39 : hun = 8'd9 ;
default : hun = 8'd0 ;
endcase
always@(*)
case(wifi_data[31:24])
8'h30 : tho = 8'd0 ;
8'h31 : tho = 8'd1 ;
8'h32 : tho = 8'd2 ;
8'h33 : tho = 8'd3 ;
8'h34 : tho = 8'd4 ;
8'h35 : tho = 8'd5 ;
8'h36 : tho = 8'd6 ;
8'h37 : tho = 8'd7 ;
8'h38 : tho = 8'd8 ;
8'h39 : tho = 8'd9 ;
default : tho = 8'd0 ;
endcase
always@(*)
case(wifi_data[39:32])
8'h30 : t_tho = 8'd0 ;
8'h31 : t_tho = 8'd1 ;
8'h32 : t_tho = 8'd2 ;
8'h33 : t_tho = 8'd3 ;
8'h34 : t_tho = 8'd4 ;
8'h35 : t_tho = 8'd5 ;
8'h36 : t_tho = 8'd6 ;
8'h37 : t_tho = 8'd7 ;
8'h38 : t_tho = 8'd8 ;
8'h39 : t_tho = 8'd9 ;
default : t_tho = 8'd0 ;
endcase
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
wifi_data <= 40'd0 ;
else if((flag == 1'b1)&&(cfg_done == 1'b1))
wifi_data <= {wifi_data[31:0],data} ;
else
wifi_data <= wifi_data ;
uart_rx
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE )
)
uart_rx_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.rx (tx_device ),
.po_data (data ),
.po_flag (flag )
);
endmodule

@ -0,0 +1,58 @@
module seg_data_ctrl
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire [39:0] seg_data ,
output reg [4:0] sel ,
output reg [7:0] dig
);
parameter CNT_DELAY_MAX = 16'd50_000 ;
reg [15:0] cnt_delay ;
wire [7:0] num[9:0] ;
assign num[0] = 8'b1100_0000 ; //0
assign num[1] = 8'b1111_1001 ; //1
assign num[2] = 8'b1010_0100 ; //2
assign num[3] = 8'b1011_0000 ; //3
assign num[4] = 8'b1001_1001 ; //4
assign num[5] = 8'b1001_0010 ; //5
assign num[6] = 8'b1000_0010 ; //6
assign num[7] = 8'b1111_1000 ; //7
assign num[8] = 8'b1000_0000 ; //8
assign num[9] = 8'b1001_0000 ; //9
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_delay <= 16'd0 ;
else if(cnt_delay == CNT_DELAY_MAX - 1'b1)
cnt_delay <= 16'd0 ;
else
cnt_delay <= cnt_delay + 1'b1 ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
sel <= 5'b11110 ;
else if((cnt_delay == CNT_DELAY_MAX - 1'b1)&&(sel == 5'b01111))
sel <= 5'b11110 ;
else if(cnt_delay == CNT_DELAY_MAX - 1'b1)
sel <= {sel[3:0],1'b1} ;
else
sel <= sel ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
dig <= 8'd0 ;
else
case(sel)
5'b11110 : dig <= num[seg_data[7:0]] ;
5'b11101 : dig <= num[seg_data[15:8]] ;
5'b11011 : dig <= num[seg_data[23:16]] ;
5'b10111 : dig <= num[seg_data[31:24]] ;
5'b01111 : dig <= num[seg_data[39:32]] ;
default : dig <= 8'd0 ;
endcase
endmodule

@ -0,0 +1,90 @@
module weather_show
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 , //
INSTR_0 = "+++" , //退
INSTR_1 = "AT+SAVETRANSLINK=0" , //
INSTR_2 = "AT+CWMODE=1" , //wifi
INSTR_3 = "AT+RST" , //
INSTR_4 = "AT+CWJAP=\"FPGA\",\"12345678\"" , //wifiwifiFPGA12345678
INSTR_5 = "AT+CIFSR" , //IP
INSTR_6 = "AT+CIPSTART=\"TCP\",\"192.168.174.107\",8888" , //TCPIP192.168.135.1078888
INSTR_7 = "AT+CIPMODE=1" , //
INSTR_8 = "AT+CIPSEND" , //
ACK_OK = "OK" , //OK
ACK_ADD = "++" , //退
ACK_END = 16'h0d0a //_+
)
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire tx_device ,
output wire rx_device ,
output wire [4:0] sel ,
output wire [7:0] dig ,
output wire [39:0] wifi_data ,
output wire [3:0] led_out ,
output wire test_rx
);
wire [39:0] seg_data ;
wire cfg_done ;
assign led_out[3:1] = 3'b000 ;
wifi_config
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE ),
.INSTR_0 (INSTR_0 ),
.INSTR_1 (INSTR_1 ),
.INSTR_2 (INSTR_2 ),
.INSTR_3 (INSTR_3 ),
.INSTR_4 (INSTR_4 ),
.INSTR_5 (INSTR_5 ),
.INSTR_6 (INSTR_6 ),
.INSTR_7 (INSTR_7 ),
.INSTR_8 (INSTR_8 ),
.ACK_OK (ACK_OK ),
.ACK_ADD (ACK_ADD ),
.ACK_END (ACK_END )
)
wifi_config_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.tx_device (tx_device ),
.rx_device (rx_device ),
.led_out (led_out[0] ),
.test_rx (test_rx ),
.test_tx ( ),
.cfg_done (cfg_done )
);
ascii_trans
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE )
)
ascii_trans_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.tx_device (tx_device ),
.cfg_done (cfg_done ),
.seg_data (seg_data ),
.wifi_data (wifi_data )
);
seg_data_ctrl seg_data_ctrl_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.seg_data (seg_data ),
.sel (sel ),
.dig (dig )
);
endmodule

@ -0,0 +1,299 @@
module esp8266_ctrl
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 , //
INSTR_0 = "+++" , //退
INSTR_1 = "AT+SAVETRANSLINK=0" , //
INSTR_2 = "AT+CWMODE=1" , //wifi
INSTR_3 = "AT+RST" , //
INSTR_4 = "AT+CWJAP=\"FPGA\",\"12345678\"" , //wifiwifiFPGA12345678
INSTR_5 = "AT+CIFSR" , //IP
INSTR_6 = "AT+CIPSTART=\"TCP\",\"192.168.135.107\",8888" , //TCPIP192.168.135.1078888
INSTR_7 = "AT+CIPMODE=1" , //
INSTR_8 = "AT+CIPSEND" , //
ACK_OK = "OK" , //OK
ACK_ADD = "++" , //退
ACK_END = 16'h0d0a //_+
)
(
input wire sys_clk , //50MHZ
input wire sys_rst_n , //
input wire [7:0] pi_data , //
input wire pi_flag , //
output reg [7:0] po_data , //
output reg po_flag , //
output reg done
);
parameter CNT_WAIT_MAX = CLK_FRE/BAUD_RATE * 10 ;
parameter CNT_DELAY_MAX = 32'd50_000_000 ;
parameter IDLE = 2'd0 ,
SEND_INSTR = 2'd1 ,
ACK = 2'd2 ;
reg [399:0] instr_data ; //
reg [5:0] instr_num ; //
reg [3:0] cnt_instr ; //
reg [5:0] cnt_bit ; //
reg [15:0] data_ack ; //
reg skip_en ; //
reg [1:0] n_state ; //
reg [1:0] c_state ; //
reg [31:0] cnt_delay ; //
reg [14:0] cnt_wait ; //
reg flag_bit ; //
reg ack_en ; //
reg ack_end ; //
reg ack_end_d ; //
wire ack_raise ; //沿
wire [7:0] data_reg[49:0] ; //
reg cfg_done ;
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
done <= 1'b0 ;
else if((pi_data == 8'h3E)&&(pi_flag == 1'b1)&&(cfg_done == 1'b1))
done <= 1'b1 ;
else
done <= done ;
assign ack_raise = ack_end & (~ack_end_d) ;
always@(*)
case(c_state)
IDLE : po_data = 8'd0 ;
SEND_INSTR : po_data = data_reg[instr_num - 1'b1 - cnt_bit] ;
ACK : po_data = 8'd0 ;
default : po_data = 8'd0 ;
endcase
always@(*)
case(c_state)
IDLE : po_flag = 1'b0 ;
SEND_INSTR : if(cnt_wait == 15'd0)
po_flag = 1'b1 ;
else
po_flag = 1'b0 ;
ACK : po_flag = 1'b0 ;
default : po_flag = 1'b0 ;
endcase
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
c_state <= IDLE ;
else
c_state <= n_state ;
always@(*)
case(c_state)
IDLE : if(skip_en == 1'b1)
n_state = SEND_INSTR ;
else
n_state = IDLE ;
SEND_INSTR : if(skip_en == 1'b1)
n_state = ACK ;
else
n_state = SEND_INSTR ;
ACK : if(skip_en == 1'b1)
n_state = IDLE ;
else
n_state = ACK ;
default : n_state = IDLE ;
endcase
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
begin
skip_en <= 1'b0 ;
cnt_instr <= 4'd0 ;
cnt_bit <= 6'd0 ;
data_ack <= 16'd0 ;
ack_en <= 1'b0 ;
ack_end <= 1'b1 ;
ack_end_d <= 1'b0 ;
cnt_delay <= 32'd0 ;
flag_bit <= 1'b0 ;
cnt_wait <= 15'd0 ;
cfg_done <= 1'b0 ;
end
else
case(c_state)
IDLE :begin
ack_en <= 1'b0 ;
cnt_wait <= 15'd0 ;
if((cnt_delay == CNT_DELAY_MAX - 1'b1)||(cfg_done == 1'b1))
cnt_delay <= 32'd0 ;
else
cnt_delay <= cnt_delay + 1'b1 ;
if(cnt_delay == CNT_DELAY_MAX - 2'd2)
skip_en <= 1'b1 ;
else
skip_en <= 1'b0 ;
end
SEND_INSTR :begin
if(cnt_wait == CNT_WAIT_MAX - 1'b1)
cnt_wait <= 15'd0 ;
else
cnt_wait <= cnt_wait + 1'b1 ;
if((cnt_wait == CNT_WAIT_MAX - 1'b1)&&(cnt_bit == instr_num - 1'b1))
cnt_bit <= 6'd0 ;
else if(cnt_wait == CNT_WAIT_MAX - 1'b1)
cnt_bit <= cnt_bit + 1'b1 ;
else
cnt_bit <= cnt_bit ;
if((cnt_wait == CNT_WAIT_MAX - 2'd2)&&(cnt_bit == instr_num - 1'b1))
skip_en <= 1'b1 ;
else
skip_en <= 1'b0 ;
end
ACK :begin
if(cnt_wait == CNT_WAIT_MAX - 1'b1)
cnt_wait <= 15'd0 ;
else
cnt_wait <= cnt_wait + 1'b1 ;
if(cnt_wait == CNT_WAIT_MAX/2 - 1'b1)
flag_bit <= 1'b1 ;
else
flag_bit <= 1'b0 ;
if(flag_bit == 1'b1)
data_ack <= {data_ack[7:0],pi_data} ;
else
data_ack <= data_ack ;
if(data_ack == ACK_OK)
ack_en <= 1'b1 ;
else
ack_en <= ack_en ;
if((data_ack == ACK_END)||((cnt_instr == 4'd0)&&(data_ack == ACK_ADD)))
ack_end <= 1'b1 ;
else
ack_end <= 1'b0 ;
ack_end_d <= ack_end ;
if((cnt_instr == 4'd8)&&(skip_en == 1'b1))
cnt_instr <= 4'd0 ;
else if(skip_en == 1'b1)
cnt_instr <= cnt_instr + 1'b1 ;
else
cnt_instr <= cnt_instr ;
if((ack_raise == 1'b1)&&(cnt_instr == 4'd0))
skip_en <= 1'b1 ;
else if((ack_raise == 1'b1)&&(ack_en == 1'b1))
skip_en <= 1'b1 ;
else
skip_en <= 1'b0 ;
if((cnt_instr == 4'd8)&&(skip_en == 1'b1))
cfg_done <= 1'b1 ;
else
cfg_done <= cfg_done ;
end
default :begin
skip_en <= 1'b0 ;
cnt_instr <= 4'd0 ;
cnt_bit <= 6'd0 ;
data_ack <= 16'd0 ;
ack_en <= 1'b0 ;
ack_end <= 1'b0 ;
ack_end_d <= 1'b0 ;
cnt_delay <= 32'd0 ;
flag_bit <= 1'b0 ;
cnt_wait <= 15'd0 ;
cfg_done <= 1'b0 ;
end
endcase
always@(*)
case(cnt_instr)
4'd0 :begin
instr_data = INSTR_0 ;
instr_num = 6'd3 ;
end
4'd1 :begin
instr_data = {INSTR_1,8'h0d,8'h0a} ;
instr_num = 6'd20 ;
end
4'd2 :begin
instr_data = {INSTR_2,8'h0d,8'h0a} ;
instr_num = 6'd13 ;
end
4'd3 :begin
instr_data = {INSTR_3,8'h0d,8'h0a} ;
instr_num = 6'd8 ;
end
4'd4 :begin
instr_data = {INSTR_4,8'h0d,8'h0a} ;
instr_num = 6'd28 ;
end
4'd5 :begin
instr_data = {INSTR_5,8'h0d,8'h0a} ;
instr_num = 6'd10 ;
end
4'd6 :begin
instr_data = {INSTR_6,8'h0d,8'h0a} ;
instr_num = 6'd42 ;
end
4'd7 :begin
instr_data = {INSTR_7,8'h0d,8'h0a} ;
instr_num = 6'd14 ;
end
4'd8 :begin
instr_data = {INSTR_8,8'h0d,8'h0a} ;
instr_num = 6'd12 ;
end
default :begin
instr_data = 400'd0 ;
instr_num = 6'd0 ;
end
endcase
assign data_reg[00] = instr_data[007:000] ;
assign data_reg[01] = instr_data[015:008] ;
assign data_reg[02] = instr_data[023:016] ;
assign data_reg[03] = instr_data[031:024] ;
assign data_reg[04] = instr_data[039:032] ;
assign data_reg[05] = instr_data[047:040] ;
assign data_reg[06] = instr_data[055:048] ;
assign data_reg[07] = instr_data[063:056] ;
assign data_reg[08] = instr_data[071:064] ;
assign data_reg[09] = instr_data[079:072] ;
assign data_reg[10] = instr_data[087:080] ;
assign data_reg[11] = instr_data[095:088] ;
assign data_reg[12] = instr_data[103:096] ;
assign data_reg[13] = instr_data[111:104] ;
assign data_reg[14] = instr_data[119:112] ;
assign data_reg[15] = instr_data[127:120] ;
assign data_reg[16] = instr_data[135:128] ;
assign data_reg[17] = instr_data[143:136] ;
assign data_reg[18] = instr_data[151:144] ;
assign data_reg[19] = instr_data[159:152] ;
assign data_reg[20] = instr_data[167:160] ;
assign data_reg[21] = instr_data[175:168] ;
assign data_reg[22] = instr_data[183:176] ;
assign data_reg[23] = instr_data[191:184] ;
assign data_reg[24] = instr_data[199:192] ;
assign data_reg[25] = instr_data[207:200] ;
assign data_reg[26] = instr_data[215:208] ;
assign data_reg[27] = instr_data[223:216] ;
assign data_reg[28] = instr_data[231:224] ;
assign data_reg[29] = instr_data[239:232] ;
assign data_reg[30] = instr_data[247:240] ;
assign data_reg[31] = instr_data[255:248] ;
assign data_reg[32] = instr_data[263:256] ;
assign data_reg[33] = instr_data[271:264] ;
assign data_reg[34] = instr_data[279:272] ;
assign data_reg[35] = instr_data[287:280] ;
assign data_reg[36] = instr_data[295:288] ;
assign data_reg[37] = instr_data[303:296] ;
assign data_reg[38] = instr_data[311:304] ;
assign data_reg[39] = instr_data[319:312] ;
assign data_reg[40] = instr_data[327:320] ;
assign data_reg[41] = instr_data[335:328] ;
assign data_reg[42] = instr_data[343:336] ;
assign data_reg[43] = instr_data[351:344] ;
assign data_reg[44] = instr_data[359:352] ;
assign data_reg[45] = instr_data[367:360] ;
assign data_reg[46] = instr_data[375:368] ;
assign data_reg[47] = instr_data[383:376] ;
assign data_reg[48] = instr_data[391:384] ;
assign data_reg[49] = instr_data[399:392] ;
endmodule

@ -0,0 +1,18 @@
module led_ctrl
(
input wire sys_clk ,
input wire sys_rst_n ,
input wire flag ,
output reg led_out
);
always@(posedge sys_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
led_out <= 1'b0 ;
else if(flag == 1'b1)
led_out <= 1'b1 ;
else
led_out <= led_out ;
endmodule

@ -0,0 +1,102 @@
module wifi_config
#(
parameter CLK_FRE = 'd50_000_000 , //
BAUD_RATE = 'd115200 , //
INSTR_0 = "+++" , //退
INSTR_1 = "AT+SAVETRANSLINK=0" , //
INSTR_2 = "AT+CWMODE=1" , //wifi
INSTR_3 = "AT+RST" , //
INSTR_4 = "AT+CWJAP=\"FPGA\",\"12345678\"" , //wifiwifiFPGA12345678
INSTR_5 = "AT+CIFSR" , //IP
INSTR_6 = "AT+CIPSTART=\"TCP\",\"192.168.135.107\",8888" , //TCPIP192.168.135.1078888
INSTR_7 = "AT+CIPMODE=1" , //
INSTR_8 = "AT+CIPSEND" , //
ACK_OK = "OK" , //OK
ACK_ADD = "++" , //退
ACK_END = 16'h0d0a //_+
)
(
input wire sys_clk , //50MHZ
input wire sys_rst_n , //
input wire tx_device , //esp8266
output wire rx_device , //esp8266
output wire led_out , //
output wire test_rx , //FPGATTL_1TX
output wire test_tx , //FPGATTL_2-TX
output wire cfg_done //
);
wire [7:0] ack_data ; //esp8266
wire ack_flag ; //
wire [7:0] cmd_data ; //FPGA
wire cmd_flag ; //
assign test_rx = tx_device ;
assign test_tx = rx_device ;
esp8266_ctrl
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE ),
.INSTR_0 (INSTR_0 ),
.INSTR_1 (INSTR_1 ),
.INSTR_2 (INSTR_2 ),
.INSTR_3 (INSTR_3 ),
.INSTR_4 (INSTR_4 ),
.INSTR_5 (INSTR_5 ),
.INSTR_6 (INSTR_6 ),
.INSTR_7 (INSTR_7 ),
.INSTR_8 (INSTR_8 ),
.ACK_OK (ACK_OK ),
.ACK_ADD (ACK_ADD ),
.ACK_END (ACK_END )
)
esp8266_ctrl
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.pi_data (ack_data ),
.pi_flag (ack_flag ),
.po_data (cmd_data ),
.po_flag (cmd_flag ),
.done (cfg_done )
);
uart_tx
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE )
)
uart_tx_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.pi_data (cmd_data ),
.pi_flag (cmd_flag ),
.tx (rx_device )
);
uart_rx
#(
.CLK_FRE (CLK_FRE ),
.BAUD_RATE (BAUD_RATE )
)
uart_rx_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.rx (tx_device ),
.po_data (ack_data ),
.po_flag (ack_flag )
);
led_ctrl led_ctrl_inst
(
.sys_clk (sys_clk ),
.sys_rst_n (sys_rst_n ),
.flag (cfg_done ),
.led_out (led_out )
);
endmodule
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