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44 lines
1.9 KiB
Plaintext
44 lines
1.9 KiB
Plaintext
5 months ago
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--lpm_add_sub CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48 DEVICE_FAMILY="Cyclone IV E" LPM_DIRECTION="SUB" LPM_WIDTH=2 cout dataa datab result
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--VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ VERSION_END
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-- Copyright (C) 2018 Intel Corporation. All rights reserved.
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-- Your use of Intel Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Intel Program License
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-- Subscription Agreement, the Intel Quartus Prime License Agreement,
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-- the Intel FPGA IP License Agreement, or other applicable license
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-- agreement, including, without limitation, that your use is for
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-- the sole purpose of programming logic devices manufactured by
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-- Intel and sold by Intel or its authorized distributors. Please
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-- refer to the applicable agreement for further details.
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--synthesis_resources =
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SUBDESIGN add_sub_8pc
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(
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cout : output;
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dataa[1..0] : input;
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datab[1..0] : input;
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result[1..0] : output;
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)
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VARIABLE
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carry_eqn[1..0] : WIRE;
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cin_wire : WIRE;
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datab_node[1..0] : WIRE;
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sum_eqn[1..0] : WIRE;
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BEGIN
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carry_eqn[] = ( ((dataa[1..1] & datab_node[1..1]) # ((dataa[1..1] # datab_node[1..1]) & carry_eqn[0..0])), ((dataa[0..0] & datab_node[0..0]) # ((dataa[0..0] # datab_node[0..0]) & cin_wire)));
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cin_wire = B"1";
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cout = carry_eqn[1..1];
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datab_node[] = (! datab[]);
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result[] = sum_eqn[];
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sum_eqn[] = ( ((dataa[1..1] $ datab_node[1..1]) $ carry_eqn[0..0]), ((dataa[0..0] $ datab_node[0..0]) $ cin_wire));
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END;
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--VALID FILE
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