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agi_fpga/hardware/prj/db/agi_fpga.sta.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1718872120522 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718872120529 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 20 16:28:39 2024 " "Processing started: Thu Jun 20 16:28:39 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718872120529 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1718872120529 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta agi_fpga -c agi_fpga " "Command: quartus_sta agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1718872120529 ""}
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1718872120678 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1718872121035 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1718872121035 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121089 ""}
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121089 ""}
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1718872121310 ""}
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718872121388 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718872121388 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1718872121388 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Timing Analyzer" 0 -1 1718872121388 ""}
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "agi_fpga.sdc " "Synopsys Design Constraints File file not found: 'agi_fpga.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1718872121404 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872121412 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872121412 "|stark_machine|sys_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872121412 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872121412 "|stark_machine|byte_num[0]"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872121421 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872121421 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718872121421 ""}
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1718872121422 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1718872121441 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 43.700 " "Worst-case setup slack is 43.700" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121478 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 43.700 0.000 altera_reserved_tck " " 43.700 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121478 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121478 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121484 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121484 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 altera_reserved_tck " " 0.452 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121484 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121484 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 96.467 " "Worst-case recovery slack is 96.467" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121491 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121491 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 96.467 0.000 altera_reserved_tck " " 96.467 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121491 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121491 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.150 " "Worst-case removal slack is 1.150" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121497 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121497 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.150 0.000 altera_reserved_tck " " 1.150 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121497 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121497 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.446 " "Worst-case minimum pulse width slack is 49.446" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121500 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.446 0.000 altera_reserved_tck " " 49.446 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872121500 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872121500 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 341.901 ns " "Worst Case Available Settling Time: 341.901 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872121597 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718872121597 ""}
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1718872121604 ""}
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1718872121666 ""}
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1718872122722 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872123000 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872123000 "|stark_machine|sys_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872123001 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872123001 "|stark_machine|byte_num[0]"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872123004 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872123004 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718872123004 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 44.105 " "Worst-case setup slack is 44.105" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123024 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 44.105 0.000 altera_reserved_tck " " 44.105 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123024 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123024 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123035 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 altera_reserved_tck " " 0.400 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123035 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123035 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 96.670 " "Worst-case recovery slack is 96.670" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123043 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 96.670 0.000 altera_reserved_tck " " 96.670 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123043 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123043 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.050 " "Worst-case removal slack is 1.050" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123050 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.050 0.000 altera_reserved_tck " " 1.050 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123050 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123050 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.299 " "Worst-case minimum pulse width slack is 49.299" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123056 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123056 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.299 0.000 altera_reserved_tck " " 49.299 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123056 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123056 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 342.553 ns " "Worst Case Available Settling Time: 342.553 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123130 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718872123130 ""}
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1718872123139 ""}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872123350 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872123350 "|stark_machine|sys_clk"}
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718872123350 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718872123350 "|stark_machine|byte_num[0]"}
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872123354 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718872123354 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718872123354 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.394 " "Worst-case setup slack is 47.394" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123363 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123363 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.394 0.000 altera_reserved_tck " " 47.394 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123363 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123363 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 altera_reserved_tck " " 0.186 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123374 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123374 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 98.347 " "Worst-case recovery slack is 98.347" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123381 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 98.347 0.000 altera_reserved_tck " " 98.347 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123381 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123381 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.505 " "Worst-case removal slack is 0.505" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123390 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123390 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.505 0.000 altera_reserved_tck " " 0.505 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123390 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123390 ""}
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.448 " "Worst-case minimum pulse width slack is 49.448" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123399 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.448 0.000 altera_reserved_tck " " 49.448 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718872123399 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718872123399 ""}
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 346.728 ns " "Worst Case Available Settling Time: 346.728 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718872123529 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718872123529 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1718872123957 ""}
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1718872123965 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4779 " "Peak virtual memory: 4779 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718872124076 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 20 16:28:44 2024 " "Processing ended: Thu Jun 20 16:28:44 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718872124076 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718872124076 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718872124076 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1718872124076 ""}