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Fitter report for agi_fpga
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Thu Jun 20 16:28:33 2024
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Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Fitter Summary
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3. Fitter Settings
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4. Parallel Compilation
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5. Incremental Compilation Preservation Summary
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6. Incremental Compilation Partition Settings
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7. Incremental Compilation Placement Preservation
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8. Pin-Out File
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9. Fitter Resource Usage Summary
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10. Fitter Partition Statistics
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11. Input Pins
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12. Output Pins
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13. Dual Purpose and Dedicated Pins
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14. I/O Bank Usage
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15. All Package Pins
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16. I/O Assignment Warnings
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17. Fitter Resource Utilization by Entity
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18. Delay Chain Summary
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19. Pad To Core Delay Chain Fanout
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20. Control Signals
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21. Global & Other Fast Signals
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22. Fitter RAM Summary
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23. Routing Usage Summary
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24. LAB Logic Elements
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25. LAB-wide Signals
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26. LAB Signals Sourced
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27. LAB Signals Sourced Out
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28. LAB Distinct Inputs
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29. I/O Rules Summary
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30. I/O Rules Details
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31. I/O Rules Matrix
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32. Fitter Device Options
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33. Operating Settings and Conditions
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34. Fitter Messages
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35. Fitter Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------------+
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; Fitter Summary ;
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+------------------------------------+---------------------------------------------+
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; Fitter Status ; Successful - Thu Jun 20 16:28:33 2024 ;
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; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
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; Revision Name ; agi_fpga ;
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; Top-level Entity Name ; stark_machine ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE6F17C8 ;
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; Timing Models ; Final ;
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; Total logic elements ; 2,715 / 6,272 ( 43 % ) ;
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; Total combinational functions ; 2,124 / 6,272 ( 34 % ) ;
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; Dedicated logic registers ; 1,320 / 6,272 ( 21 % ) ;
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; Total registers ; 1320 ;
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; Total pins ; 24 / 180 ( 13 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 102,400 / 276,480 ( 37 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
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; Total PLLs ; 0 / 2 ( 0 % ) ;
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+------------------------------------+---------------------------------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Settings ;
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+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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; Option ; Setting ; Default Value ;
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+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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; Device ; EP4CE6F17C8 ; ;
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; Nominal Core Supply Voltage ; 1.2V ; ;
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; Minimum Core Junction Temperature ; 0 ; ;
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; Maximum Core Junction Temperature ; 85 ; ;
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; Fit Attempts to Skip ; 0 ; 0.0 ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Auto Merge PLLs ; On ; On ;
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; Router Timing Optimization Level ; Normal ; Normal ;
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; Perform Clocking Topology Analysis During Routing ; Off ; Off ;
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; Placement Effort Multiplier ; 1.0 ; 1.0 ;
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; Router Effort Multiplier ; 1.0 ; 1.0 ;
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; Optimize Hold Timing ; All Paths ; All Paths ;
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; Optimize Multi-Corner Timing ; On ; On ;
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; Power Optimization During Fitting ; Normal compilation ; Normal compilation ;
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; SSN Optimization ; Off ; Off ;
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; Optimize Timing ; Normal compilation ; Normal compilation ;
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; Optimize Timing for ECOs ; Off ; Off ;
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; Regenerate Full Fit Report During ECO Compiles ; Off ; Off ;
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; Optimize IOC Register Placement for Timing ; Normal ; Normal ;
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; Limit to One Fitting Attempt ; Off ; Off ;
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; Final Placement Optimizations ; Automatically ; Automatically ;
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; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
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; Fitter Initial Placement Seed ; 1 ; 1 ;
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; Periphery to Core Placement and Routing Optimization ; Off ; Off ;
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; PCI I/O ; Off ; Off ;
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; Weak Pull-Up Resistor ; Off ; Off ;
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; Enable Bus-Hold Circuitry ; Off ; Off ;
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; Auto Packed Registers ; Auto ; Auto ;
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; Auto Delay Chains ; On ; On ;
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; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ;
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; Allow Single-ended Buffer for Differential-XSTL Input ; Off ; Off ;
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; Treat Bidirectional Pin as Output Pin ; Off ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ;
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; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ;
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; Perform Register Duplication for Performance ; Off ; Off ;
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; Perform Logic to Memory Mapping for Fitting ; Off ; Off ;
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; Perform Register Retiming for Performance ; Off ; Off ;
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; Perform Asynchronous Signal Pipelining ; Off ; Off ;
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; Fitter Effort ; Auto Fit ; Auto Fit ;
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; Physical Synthesis Effort Level ; Normal ; Normal ;
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; Logic Cell Insertion - Logic Duplication ; Auto ; Auto ;
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; Auto Register Duplication ; Auto ; Auto ;
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; Auto Global Clock ; On ; On ;
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; Auto Global Register Control Signals ; On ; On ;
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; Reserve all unused pins ; As input tri-stated with weak pull-up ; As input tri-stated with weak pull-up ;
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; Synchronizer Identification ; Auto ; Auto ;
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; Enable Beneficial Skew Optimization ; On ; On ;
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; Optimize Design for Metastability ; On ; On ;
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; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
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; Enable input tri-state on active configuration pins in user mode ; Off ; Off ;
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+--------------------------------------------------------------------+---------------------------------------+---------------------------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.07 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 2.5% ;
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; Processor 3 ; 2.4% ;
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; Processor 4 ; 2.3% ;
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+----------------------------+-------------+
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+---------------------------------------------------------------------------------------------------+
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; Incremental Compilation Preservation Summary ;
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+---------------------+---------------------+----------------------------+--------------------------+
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; Type ; Total [A + B] ; From Design Partitions [A] ; From Rapid Recompile [B] ;
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+---------------------+---------------------+----------------------------+--------------------------+
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; Placement (by node) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 3562 ) ; 0.00 % ( 0 / 3562 ) ; 0.00 % ( 0 / 3562 ) ;
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; -- Achieved ; 0.00 % ( 0 / 3562 ) ; 0.00 % ( 0 / 3562 ) ; 0.00 % ( 0 / 3562 ) ;
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; ; ; ; ;
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; Routing (by net) ; ; ; ;
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; -- Requested ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
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; -- Achieved ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ; 0.00 % ( 0 / 0 ) ;
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+---------------------+---------------------+----------------------------+--------------------------+
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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Incremental Compilation Partition Settings ;
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+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
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; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
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+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
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; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ;
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; sld_hub:auto_hub ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_hub:auto_hub ;
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; sld_signaltap:auto_signaltap_0 ; Auto-generated ; Post-Synthesis ; N/A ; Post-Synthesis ; N/A ; sld_signaltap:auto_signaltap_0 ;
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; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ;
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+--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+
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+------------------------------------------------------------------------------------------------------------------------------------+
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; Incremental Compilation Placement Preservation ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Partition Name ; Preservation Achieved ; Preservation Level Used ; Netlist Type Used ; Preservation Method ; Notes ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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; Top ; 0.00 % ( 0 / 1820 ) ; N/A ; Source File ; N/A ; ;
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; sld_hub:auto_hub ; 0.00 % ( 0 / 219 ) ; N/A ; Post-Synthesis ; N/A ; ;
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; sld_signaltap:auto_signaltap_0 ; 0.00 % ( 0 / 1515 ) ; N/A ; Post-Synthesis ; N/A ; ;
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; hard_block:auto_generated_inst ; 0.00 % ( 0 / 8 ) ; N/A ; Source File ; N/A ; ;
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+--------------------------------+-----------------------+-------------------------+-------------------+---------------------+-------+
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+--------------+
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; Pin-Out File ;
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+--------------+
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The pin-out file can be found in C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.pin.
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+--------------------------------------------------------------------------+
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; Fitter Resource Usage Summary ;
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+---------------------------------------------+----------------------------+
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; Resource ; Usage ;
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+---------------------------------------------+----------------------------+
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; Total logic elements ; 2,715 / 6,272 ( 43 % ) ;
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; -- Combinational with no register ; 1395 ;
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; -- Register only ; 591 ;
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; -- Combinational with a register ; 729 ;
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; ; ;
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; Logic element usage by number of LUT inputs ; ;
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; -- 4 input functions ; 689 ;
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; -- 3 input functions ; 536 ;
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; -- <=2 input functions ; 899 ;
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; -- Register only ; 591 ;
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; ; ;
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; Logic elements by mode ; ;
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; -- normal mode ; 1569 ;
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; -- arithmetic mode ; 555 ;
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; ; ;
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; Total registers* ; 1,320 / 7,124 ( 19 % ) ;
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; -- Dedicated logic registers ; 1,320 / 6,272 ( 21 % ) ;
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; -- I/O registers ; 0 / 852 ( 0 % ) ;
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; ; ;
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; Total LABs: partially or completely used ; 222 / 392 ( 57 % ) ;
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; Virtual pins ; 0 ;
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; I/O pins ; 24 / 180 ( 13 % ) ;
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; -- Clock pins ; 3 / 3 ( 100 % ) ;
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; -- Dedicated input pins ; 3 / 9 ( 33 % ) ;
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; ; ;
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; M9Ks ; 13 / 30 ( 43 % ) ;
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; Total block memory bits ; 102,400 / 276,480 ( 37 % ) ;
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; Total block memory implementation bits ; 119,808 / 276,480 ( 43 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
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; PLLs ; 0 / 2 ( 0 % ) ;
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; Global signals ; 4 ;
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; -- Global clocks ; 4 / 10 ( 40 % ) ;
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; JTAGs ; 1 / 1 ( 100 % ) ;
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; CRC blocks ; 0 / 1 ( 0 % ) ;
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; ASMI blocks ; 0 / 1 ( 0 % ) ;
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; Oscillator blocks ; 0 / 1 ( 0 % ) ;
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; Impedance control blocks ; 0 / 4 ( 0 % ) ;
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; Average interconnect usage (total/H/V) ; 4.6% / 4.5% / 4.8% ;
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; Peak interconnect usage (total/H/V) ; 9.3% / 8.5% / 10.5% ;
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; Maximum fan-out ; 836 ;
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; Highest non-global fan-out ; 175 ;
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; Total fan-out ; 11203 ;
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; Average fan-out ; 2.83 ;
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+---------------------------------------------+----------------------------+
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* Register count does not include registers inside RAM blocks or DSP blocks.
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Partition Statistics ;
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+---------------------------------------------+----------------------+--------------------+--------------------------------+--------------------------------+
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; Statistic ; Top ; sld_hub:auto_hub ; sld_signaltap:auto_signaltap_0 ; hard_block:auto_generated_inst ;
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+---------------------------------------------+----------------------+--------------------+--------------------------------+--------------------------------+
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; Difficulty Clustering Region ; Low ; Low ; Low ; Low ;
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; ; ; ; ; ;
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; Total logic elements ; 1489 / 6272 ( 24 % ) ; 149 / 6272 ( 2 % ) ; 1077 / 6272 ( 17 % ) ; 0 / 6272 ( 0 % ) ;
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; -- Combinational with no register ; 1210 ; 58 ; 127 ; 0 ;
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; -- Register only ; 9 ; 21 ; 561 ; 0 ;
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; -- Combinational with a register ; 270 ; 70 ; 389 ; 0 ;
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; ; ; ; ; ;
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; Logic element usage by number of LUT inputs ; ; ; ; ;
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; -- 4 input functions ; 408 ; 53 ; 228 ; 0 ;
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; -- 3 input functions ; 341 ; 38 ; 157 ; 0 ;
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; -- <=2 input functions ; 731 ; 37 ; 131 ; 0 ;
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; -- Register only ; 9 ; 21 ; 561 ; 0 ;
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; ; ; ; ; ;
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; Logic elements by mode ; ; ; ; ;
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; -- normal mode ; 1017 ; 120 ; 432 ; 0 ;
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; -- arithmetic mode ; 463 ; 8 ; 84 ; 0 ;
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; ; ; ; ; ;
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; Total registers ; 279 ; 91 ; 950 ; 0 ;
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; -- Dedicated logic registers ; 279 / 6272 ( 4 % ) ; 91 / 6272 ( 1 % ) ; 950 / 6272 ( 15 % ) ; 0 / 6272 ( 0 % ) ;
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; -- I/O registers ; 0 ; 0 ; 0 ; 0 ;
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; ; ; ; ; ;
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; Total LABs: partially or completely used ; 113 / 392 ( 29 % ) ; 13 / 392 ( 3 % ) ; 103 / 392 ( 26 % ) ; 0 / 392 ( 0 % ) ;
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; ; ; ; ; ;
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; Virtual pins ; 0 ; 0 ; 0 ; 0 ;
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; I/O pins ; 24 ; 0 ; 0 ; 0 ;
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; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ;
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; Total memory bits ; 0 ; 0 ; 102400 ; 0 ;
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; Total RAM block bits ; 0 ; 0 ; 119808 ; 0 ;
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; JTAG ; 1 / 1 ( 100 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ; 0 / 1 ( 0 % ) ;
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; M9K ; 0 / 30 ( 0 % ) ; 0 / 30 ( 0 % ) ; 13 / 30 ( 43 % ) ; 0 / 30 ( 0 % ) ;
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; Clock control block ; 3 / 12 ( 25 % ) ; 0 / 12 ( 0 % ) ; 1 / 12 ( 8 % ) ; 0 / 12 ( 0 % ) ;
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; ; ; ; ; ;
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; Connections ; ; ; ; ;
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; -- Input Connections ; 1 ; 134 ; 1267 ; 0 ;
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; -- Registered Input Connections ; 0 ; 102 ; 1015 ; 0 ;
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; -- Output Connections ; 1204 ; 164 ; 34 ; 0 ;
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; -- Registered Output Connections ; 52 ; 164 ; 0 ; 0 ;
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; ; ; ; ; ;
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; Internal Connections ; ; ; ; ;
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; -- Total Connections ; 6490 ; 869 ; 5224 ; 4 ;
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; -- Registered Connections ; 1206 ; 625 ; 2856 ; 0 ;
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; ; ; ; ; ;
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; External Connections ; ; ; ; ;
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; -- Top ; 0 ; 123 ; 1082 ; 0 ;
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; -- sld_hub:auto_hub ; 123 ; 20 ; 155 ; 0 ;
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; -- sld_signaltap:auto_signaltap_0 ; 1082 ; 155 ; 64 ; 0 ;
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; -- hard_block:auto_generated_inst ; 0 ; 0 ; 0 ; 0 ;
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; ; ; ; ; ;
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; Partition Interface ; ; ; ; ;
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; -- Input Ports ; 6 ; 45 ; 219 ; 0 ;
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; -- Output Ports ; 72 ; 62 ; 115 ; 0 ;
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; -- Bidir Ports ; 0 ; 0 ; 0 ; 0 ;
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; ; ; ; ; ;
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; Registered Ports ; ; ; ; ;
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; -- Registered Input Ports ; 0 ; 4 ; 40 ; 0 ;
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; -- Registered Output Ports ; 0 ; 29 ; 101 ; 0 ;
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; ; ; ; ; ;
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; Port Connectivity ; ; ; ; ;
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; -- Input Ports driven by GND ; 0 ; 0 ; 22 ; 0 ;
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; -- Output Ports driven by GND ; 0 ; 28 ; 2 ; 0 ;
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; -- Input Ports driven by VCC ; 0 ; 0 ; 10 ; 0 ;
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; -- Output Ports driven by VCC ; 0 ; 0 ; 1 ; 0 ;
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; -- Input Ports with no Source ; 0 ; 25 ; 54 ; 0 ;
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; -- Output Ports with no Source ; 0 ; 0 ; 0 ; 0 ;
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; -- Input Ports with no Fanout ; 0 ; 30 ; 68 ; 0 ;
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; -- Output Ports with no Fanout ; 0 ; 29 ; 103 ; 0 ;
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+---------------------------------------------+----------------------+--------------------+--------------------------------+--------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Input Pins ;
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+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination Control Block ; Location assigned by ; Slew Rate ;
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+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
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; rx ; M2 ; 2 ; 0 ; 11 ; 14 ; 1 ; 0 ; no ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
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; sys_clk ; E1 ; 1 ; 0 ; 11 ; 7 ; 836 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
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; sys_rst_n ; E15 ; 6 ; 34 ; 12 ; 0 ; 263 ; 0 ; yes ; no ; no ; yes ; no ; Off ; 2.5 V ; -- ; User ; no ;
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+-----------+-------+----------+--------------+--------------+--------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+---------------------------+----------------------+-----------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Output Pins ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
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; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Z coordinate ; Output Register ; Output Enable Register ; Power Up High ; Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Termination Control Block ; Output Buffer Pre-emphasis ; Voltage Output Differential ; Location assigned by ; Output Enable Source ; Output Enable Group ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
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; beep ; J1 ; 2 ; 0 ; 10 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; dout ; K6 ; 2 ; 0 ; 9 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; led[0] ; G15 ; 6 ; 34 ; 17 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; led[1] ; F16 ; 6 ; 34 ; 18 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; led[2] ; F15 ; 6 ; 34 ; 18 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; led[3] ; D16 ; 6 ; 34 ; 19 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[0] ; B7 ; 8 ; 11 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[1] ; A8 ; 8 ; 16 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[2] ; A6 ; 8 ; 9 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[3] ; B5 ; 8 ; 5 ; 24 ; 7 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[4] ; B6 ; 8 ; 9 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[5] ; A7 ; 8 ; 11 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[6] ; B8 ; 8 ; 16 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; seg_led[7] ; A5 ; 8 ; 7 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[0] ; A4 ; 8 ; 5 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[1] ; B4 ; 8 ; 5 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[2] ; A3 ; 8 ; 3 ; 24 ; 14 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[3] ; B3 ; 8 ; 3 ; 24 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[4] ; A2 ; 8 ; 5 ; 24 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; sel_led[5] ; B1 ; 1 ; 0 ; 22 ; 0 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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; tx ; G1 ; 1 ; 0 ; 18 ; 21 ; no ; no ; no ; 2 ; no ; no ; no ; no ; Off ; 2.5 V ; Default ; Series 50 Ohm without Calibration ; -- ; no ; no ; User ; - ; - ;
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+------------+-------+----------+--------------+--------------+--------------+-----------------+------------------------+---------------+-----------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-----------------------------------+---------------------------+----------------------------+-----------------------------+----------------------+----------------------+---------------------+
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+-------------------------------------------------------------------------------------------------------------------------+
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; Dual Purpose and Dedicated Pins ;
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+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
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; Location ; Pin Name ; Reserved As ; User Signal Name ; Pin Type ;
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+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
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; C1 ; DIFFIO_L1n, DATA1, ASDO ; As input tri-stated ; ~ALTERA_ASDO_DATA1~ ; Dual Purpose Pin ;
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; D2 ; DIFFIO_L2p, FLASH_nCE, nCSO ; As input tri-stated ; ~ALTERA_FLASH_nCE_nCSO~ ; Dual Purpose Pin ;
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; F4 ; nSTATUS ; - ; - ; Dedicated Programming Pin ;
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; H1 ; DCLK ; As output driving ground ; ~ALTERA_DCLK~ ; Dual Purpose Pin ;
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; H2 ; DATA0 ; As input tri-stated ; ~ALTERA_DATA0~ ; Dual Purpose Pin ;
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; H5 ; nCONFIG ; - ; - ; Dedicated Programming Pin ;
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; H4 ; TDI ; - ; altera_reserved_tdi ; JTAG Pin ;
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; H3 ; TCK ; - ; altera_reserved_tck ; JTAG Pin ;
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; J5 ; TMS ; - ; altera_reserved_tms ; JTAG Pin ;
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; J4 ; TDO ; - ; altera_reserved_tdo ; JTAG Pin ;
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; J3 ; nCE ; - ; - ; Dedicated Programming Pin ;
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; H14 ; CONF_DONE ; - ; - ; Dedicated Programming Pin ;
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; H13 ; MSEL0 ; - ; - ; Dedicated Programming Pin ;
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; H12 ; MSEL1 ; - ; - ; Dedicated Programming Pin ;
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; G12 ; MSEL2 ; - ; - ; Dedicated Programming Pin ;
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; G12 ; MSEL3 ; - ; - ; Dedicated Programming Pin ;
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; G15 ; DIFFIO_R4p, CRC_ERROR ; Use as regular IO ; led[0] ; Dual Purpose Pin ;
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; F16 ; DIFFIO_R3n, nCEO ; Use as programming pin ; led[1] ; Dual Purpose Pin ;
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; F15 ; DIFFIO_R3p, CLKUSR ; Use as regular IO ; led[2] ; Dual Purpose Pin ;
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; B7 ; DIFFIO_T9p, DATA4 ; Use as regular IO ; seg_led[0] ; Dual Purpose Pin ;
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; A5 ; DIFFIO_T6n, DATA7 ; Use as regular IO ; seg_led[7] ; Dual Purpose Pin ;
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+----------+-----------------------------+--------------------------+-------------------------+---------------------------+
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+------------------------------------------------------------+
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; I/O Bank Usage ;
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+----------+------------------+---------------+--------------+
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; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
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+----------+------------------+---------------+--------------+
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; 1 ; 7 / 17 ( 41 % ) ; 2.5V ; -- ;
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; 2 ; 3 / 19 ( 16 % ) ; 2.5V ; -- ;
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; 3 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ;
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; 4 ; 0 / 27 ( 0 % ) ; 2.5V ; -- ;
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; 5 ; 0 / 25 ( 0 % ) ; 2.5V ; -- ;
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; 6 ; 5 / 14 ( 36 % ) ; 2.5V ; -- ;
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; 7 ; 0 / 26 ( 0 % ) ; 2.5V ; -- ;
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; 8 ; 13 / 26 ( 50 % ) ; 2.5V ; -- ;
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+----------+------------------+---------------+--------------+
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+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; All Package Pins ;
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+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
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; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ;
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+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
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; A1 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; A2 ; 194 ; 8 ; sel_led[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A3 ; 200 ; 8 ; sel_led[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A4 ; 196 ; 8 ; sel_led[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A5 ; 192 ; 8 ; seg_led[7] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A6 ; 188 ; 8 ; seg_led[2] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A7 ; 183 ; 8 ; seg_led[5] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A8 ; 177 ; 8 ; seg_led[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; A9 ; 175 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A10 ; 168 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A11 ; 161 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A12 ; 159 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A13 ; 153 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A14 ; 155 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A15 ; 167 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; A16 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; B1 ; 3 ; 1 ; sel_led[5] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; B3 ; 201 ; 8 ; sel_led[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B4 ; 197 ; 8 ; sel_led[1] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B5 ; 195 ; 8 ; seg_led[3] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B6 ; 189 ; 8 ; seg_led[4] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B7 ; 184 ; 8 ; seg_led[0] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B8 ; 178 ; 8 ; seg_led[6] ; output ; 2.5 V ; ; Column I/O ; Y ; no ; Off ;
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; B9 ; 176 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B10 ; 169 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B11 ; 162 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B12 ; 160 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B13 ; 154 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B14 ; 156 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; B15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; B16 ; 141 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; C1 ; 5 ; 1 ; ~ALTERA_ASDO_DATA1~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
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; C2 ; 4 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; C3 ; 202 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; C4 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; C6 ; 187 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
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; C7 ; ; 8 ; VCCIO8 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; C8 ; 179 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; C9 ; 172 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; C10 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; C11 ; 163 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
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; C12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; C13 ; ; 7 ; VCCIO7 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; C14 ; 149 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; C15 ; 147 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; C16 ; 146 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; D1 ; 8 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; D2 ; 7 ; 1 ; ~ALTERA_FLASH_nCE_nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
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; D3 ; 203 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D4 ; 0 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; D5 ; 198 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D6 ; 199 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; D8 ; 180 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D9 ; 173 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; D11 ; 151 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D12 ; 152 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D13 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; D14 ; 150 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; D15 ; 144 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; D16 ; 143 ; 6 ; led[3] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; E1 ; 24 ; 1 ; sys_clk ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; E2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; E3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; E4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; E5 ; 1 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; E6 ; 191 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E7 ; 190 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E8 ; 181 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E9 ; 174 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E10 ; 158 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E11 ; 157 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; E12 ; ; ; GNDA2 ; gnd ; ; ; -- ; ; -- ; -- ;
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; E13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; E14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; E15 ; 128 ; 6 ; sys_rst_n ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; E16 ; 127 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
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; F1 ; 12 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; F2 ; 11 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; F3 ; 6 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
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; F4 ; 9 ; 1 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
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|
; F5 ; 2 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; F6 ; 185 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F7 ; 186 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F8 ; 182 ; 8 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F9 ; 165 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F10 ; 164 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F11 ; 166 ; 7 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; F12 ; ; -- ; VCCA2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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|
; F13 ; 138 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; F14 ; 142 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
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; F15 ; 140 ; 6 ; led[2] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; F16 ; 139 ; 6 ; led[1] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; G1 ; 14 ; 1 ; tx ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; G2 ; 13 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; G3 ; ; 1 ; VCCIO1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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|
; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; G5 ; 10 ; 1 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; G6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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|
; G7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; G8 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; G9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; G10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
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; G11 ; 145 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
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; G12 ; 132 ; 6 ; ^MSEL2 ; ; ; ; -- ; ; -- ; -- ;
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|
|
; G12 ; 133 ; 6 ; ^MSEL3 ; ; ; ; -- ; ; -- ; -- ;
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|
|
; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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|
|
; G14 ; ; 6 ; VCCIO6 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
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|
|
; G15 ; 137 ; 6 ; led[0] ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
|
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|
; G16 ; 136 ; 6 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
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|
|
; H1 ; 15 ; 1 ; ~ALTERA_DCLK~ ; output ; 2.5 V ; ; Row I/O ; N ; no ; On ;
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; H2 ; 16 ; 1 ; ~ALTERA_DATA0~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 2.5 V ; ; Row I/O ; N ; no ; On ;
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|
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|
|
; H3 ; 19 ; 1 ; altera_reserved_tck ; input ; 2.5 V ; ; -- ; N ; no ; Off ;
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|
|
; H4 ; 18 ; 1 ; altera_reserved_tdi ; input ; 2.5 V ; ; -- ; N ; no ; Off ;
|
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|
|
; H5 ; 17 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
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|
|
; H6 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
|
|
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|
|
; H7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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|
|
; H8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
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|
|
; H9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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|
|
; H10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
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|
|
; H11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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|
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|
|
; H12 ; 131 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
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|
|
; H13 ; 130 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ;
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|
; H14 ; 129 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
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|
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|
|
; H15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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|
|
; H16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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|
|
; J1 ; 28 ; 2 ; beep ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
|
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|
|
; J2 ; 27 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
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|
|
; J3 ; 22 ; 1 ; ^nCE ; ; ; ; -- ; ; -- ; -- ;
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|
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|
|
; J4 ; 21 ; 1 ; altera_reserved_tdo ; output ; 2.5 V ; ; -- ; N ; no ; Off ;
|
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|
|
; J5 ; 20 ; 1 ; altera_reserved_tms ; input ; 2.5 V ; ; -- ; N ; no ; Off ;
|
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|
; J6 ; 29 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; J8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
|
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|
|
; J9 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
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|
|
; J10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
|
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|
|
; J11 ; 117 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J12 ; 123 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J13 ; 124 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J14 ; 122 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J15 ; 121 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; J16 ; 120 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
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|
|
; K1 ; 33 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
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|
|
; K2 ; 32 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; K3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; K4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
|
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|
|
; K5 ; 39 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; K6 ; 30 ; 2 ; dout ; output ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
|
|
|
|
|
|
; K7 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; K8 ; 60 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; K9 ; 76 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; K10 ; 87 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; K11 ; 110 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; K12 ; 105 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; K14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; K15 ; 119 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; K16 ; 118 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L1 ; 35 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L2 ; 34 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L3 ; 36 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
|
|
|
|
|
; L4 ; 40 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L5 ; ; -- ; VCCA1 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
|
|
|
|
|
|
; L6 ; 31 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L7 ; 65 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; L8 ; 68 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; L9 ; 77 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; L10 ; 88 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; L11 ; 99 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
|
|
|
|
|
|
; L12 ; 104 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L13 ; 114 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L14 ; 113 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; -- ; -- ;
|
|
|
|
|
|
; L15 ; 116 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; L16 ; 115 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
|
|
|
|
|
|
; M1 ; 26 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
|
|
|
|
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; M2 ; 25 ; 2 ; rx ; input ; 2.5 V ; ; Row I/O ; Y ; no ; Off ;
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; M3 ; ; 2 ; VCCIO2 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; M5 ; ; ; GNDA1 ; gnd ; ; ; -- ; ; -- ; -- ;
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; M6 ; 57 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M7 ; 59 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M8 ; 69 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M9 ; 78 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M10 ; 93 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M11 ; 100 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; M12 ; 103 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; M14 ; ; 5 ; VCCIO5 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; M15 ; 126 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
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; M16 ; 125 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ;
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; N1 ; 38 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; N2 ; 37 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; N3 ; 45 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N4 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ;
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; N5 ; 55 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N6 ; 56 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; N8 ; 70 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N9 ; 79 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; N11 ; 94 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N12 ; 101 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; N13 ; 102 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; N14 ; 106 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; N15 ; 112 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; N16 ; 111 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; P1 ; 44 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; P2 ; 43 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; P3 ; 46 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; P4 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; P5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; P6 ; 58 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
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; P7 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; P8 ; 71 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; P9 ; 89 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; P10 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; P11 ; 90 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; -- ; -- ;
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; P12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; P13 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; P14 ; 98 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; P15 ; 107 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; P16 ; 108 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; R1 ; 42 ; 2 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; R2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; R3 ; 47 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R4 ; 53 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R5 ; 61 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R6 ; 63 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R7 ; 66 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R8 ; 72 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R9 ; 74 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R10 ; 80 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R11 ; 83 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R12 ; 85 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R13 ; 91 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R14 ; 97 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; R15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
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; R16 ; 109 ; 5 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Row I/O ; ; no ; On ;
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; T1 ; ; 3 ; VCCIO3 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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; T2 ; 52 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T3 ; 48 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T4 ; 54 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T5 ; 62 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T6 ; 64 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T7 ; 67 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T8 ; 73 ; 3 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T9 ; 75 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T10 ; 81 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T11 ; 84 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T12 ; 86 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T13 ; 92 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T14 ; 95 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T15 ; 96 ; 4 ; RESERVED_INPUT_WITH_WEAK_PULLUP ; ; ; ; Column I/O ; ; no ; On ;
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; T16 ; ; 4 ; VCCIO4 ; power ; ; 2.5V ; -- ; ; -- ; -- ;
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+----------+------------+----------+-----------------------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+
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Note: Pin directions (input, output or bidir) are based on device operating in user mode.
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+--------------------------------------------+
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; I/O Assignment Warnings ;
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+------------+-------------------------------+
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; Pin Name ; Reason ;
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+------------+-------------------------------+
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; tx ; Incomplete set of assignments ;
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; led[0] ; Incomplete set of assignments ;
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; led[1] ; Incomplete set of assignments ;
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; led[2] ; Incomplete set of assignments ;
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; led[3] ; Incomplete set of assignments ;
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; beep ; Incomplete set of assignments ;
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; seg_led[0] ; Incomplete set of assignments ;
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; seg_led[1] ; Incomplete set of assignments ;
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; seg_led[2] ; Incomplete set of assignments ;
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; seg_led[3] ; Incomplete set of assignments ;
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; seg_led[4] ; Incomplete set of assignments ;
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; seg_led[5] ; Incomplete set of assignments ;
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; seg_led[6] ; Incomplete set of assignments ;
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; seg_led[7] ; Incomplete set of assignments ;
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; sel_led[0] ; Incomplete set of assignments ;
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; sel_led[1] ; Incomplete set of assignments ;
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; sel_led[2] ; Incomplete set of assignments ;
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; sel_led[3] ; Incomplete set of assignments ;
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; sel_led[4] ; Incomplete set of assignments ;
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; sel_led[5] ; Incomplete set of assignments ;
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; dout ; Incomplete set of assignments ;
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; sys_clk ; Incomplete set of assignments ;
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; sys_rst_n ; Incomplete set of assignments ;
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; rx ; Incomplete set of assignments ;
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+------------+-------------------------------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Fitter Resource Utilization by Entity ;
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+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
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; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M9Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Entity Name ; Library Name ;
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+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
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; |stark_machine ; 2715 (39) ; 1320 (26) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 24 ; 0 ; 1395 (13) ; 591 (3) ; 729 (13) ; |stark_machine ; stark_machine ; work ;
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; |circuit_arb:circuit_arb_inst| ; 1370 (3) ; 198 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1162 (2) ; 1 (0) ; 207 (1) ; |stark_machine|circuit_arb:circuit_arb_inst ; circuit_arb ; work ;
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; |beep_circuit:beep_circuit_inst| ; 139 (0) ; 48 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 88 (0) ; 0 (0) ; 51 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst ; beep_circuit ; work ;
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; |freq_select:freq_select_inst| ; 139 (139) ; 47 (47) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 88 (88) ; 0 (0) ; 51 (51) ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst ; freq_select ; work ;
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; |pwm_beep:pwm_beep_inst| ; 1 (1) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|pwm_beep:pwm_beep_inst ; pwm_beep ; work ;
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; |clock_circuit:clock_circuit_inst| ; 1045 (0) ; 63 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 982 (0) ; 1 (0) ; 62 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst ; clock_circuit ; work ;
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; |timer:timer_inst| ; 799 (64) ; 46 (46) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 753 (18) ; 0 (0) ; 46 (46) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst ; timer ; work ;
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; |lpm_divide:Div0| ; 176 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0 ; lpm_divide ; work ;
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; |lpm_divide_ikm:auto_generated| ; 176 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated ; lpm_divide_ikm ; work ;
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; |sign_div_unsign_anh:divider| ; 176 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated|sign_div_unsign_anh:divider ; sign_div_unsign_anh ; work ;
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; |alt_u_div_8af:divider| ; 176 (176) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 176 (176) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated|sign_div_unsign_anh:divider|alt_u_div_8af:divider ; alt_u_div_8af ; work ;
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; |lpm_divide:Div1| ; 122 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1 ; lpm_divide ; work ;
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; |lpm_divide_0jm:auto_generated| ; 122 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated ; lpm_divide_0jm ; work ;
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; |sign_div_unsign_olh:divider| ; 122 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated|sign_div_unsign_olh:divider ; sign_div_unsign_olh ; work ;
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; |alt_u_div_47f:divider| ; 122 (122) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 122 (122) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_47f:divider ; alt_u_div_47f ; work ;
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; |lpm_divide:Mod0| ; 211 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0 ; lpm_divide ; work ;
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; |lpm_divide_lcm:auto_generated| ; 211 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated ; lpm_divide_lcm ; work ;
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; |sign_div_unsign_anh:divider| ; 211 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated|sign_div_unsign_anh:divider ; sign_div_unsign_anh ; work ;
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; |alt_u_div_8af:divider| ; 211 (211) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 211 (211) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated|sign_div_unsign_anh:divider|alt_u_div_8af:divider ; alt_u_div_8af ; work ;
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; |lpm_divide:Mod1| ; 226 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 226 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1 ; lpm_divide ; work ;
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; |lpm_divide_8bm:auto_generated| ; 226 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 226 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated ; lpm_divide_8bm ; work ;
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; |sign_div_unsign_tlh:divider| ; 226 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 226 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated|sign_div_unsign_tlh:divider ; sign_div_unsign_tlh ; work ;
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; |alt_u_div_e7f:divider| ; 226 (226) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 226 (226) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated|sign_div_unsign_tlh:divider|alt_u_div_e7f:divider ; alt_u_div_e7f ; work ;
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; |timer_decoder:timer_decoder_inst| ; 247 (78) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 229 (60) ; 1 (1) ; 17 (17) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst ; timer_decoder ; work ;
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; |lpm_divide:Div0| ; 18 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0 ; lpm_divide ; work ;
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; |lpm_divide_ghm:auto_generated| ; 18 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated ; lpm_divide_ghm ; work ;
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; |sign_div_unsign_8kh:divider| ; 18 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated|sign_div_unsign_8kh:divider ; sign_div_unsign_8kh ; work ;
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; |alt_u_div_44f:divider| ; 18 (18) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 18 (18) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider ; alt_u_div_44f ; work ;
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; |lpm_divide:Div1| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1 ; lpm_divide ; work ;
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; |lpm_divide_hhm:auto_generated| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated ; lpm_divide_hhm ; work ;
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; |sign_div_unsign_9kh:divider| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Div2| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2 ; lpm_divide ; work ;
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; |lpm_divide_hhm:auto_generated| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated ; lpm_divide_hhm ; work ;
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; |sign_div_unsign_9kh:divider| ; 32 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 32 (32) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Mod0| ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0 ; lpm_divide ; work ;
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; |lpm_divide_j9m:auto_generated| ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated ; lpm_divide_j9m ; work ;
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; |sign_div_unsign_8kh:divider| ; 21 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider ; sign_div_unsign_8kh ; work ;
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; |alt_u_div_44f:divider| ; 21 (21) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 21 (21) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider ; alt_u_div_44f ; work ;
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; |lpm_divide:Mod1| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1 ; lpm_divide ; work ;
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; |lpm_divide_k9m:auto_generated| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated ; lpm_divide_k9m ; work ;
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; |sign_div_unsign_9kh:divider| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Mod2| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2 ; lpm_divide ; work ;
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; |lpm_divide_k9m:auto_generated| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated ; lpm_divide_k9m ; work ;
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; |sign_div_unsign_9kh:divider| ; 33 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (0) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 33 (33) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 33 (33) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |led_circuit:led_circuit_inst| ; 67 (67) ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 29 (29) ; 0 (0) ; 38 (38) ; |stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst ; led_circuit ; work ;
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; |ws2812_circuit:ws2812_circuit_inst| ; 116 (0) ; 54 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 61 (0) ; 0 (0) ; 55 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst ; ws2812_circuit ; work ;
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; |data_cfg:data_cfg_inst| ; 23 (23) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 23 (23) ; 0 (0) ; 0 (0) ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|data_cfg:data_cfg_inst ; data_cfg ; work ;
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; |ws2812_ctrl:ws2812_ctrl_inst| ; 93 (93) ; 54 (54) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 38 (38) ; 0 (0) ; 55 (55) ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst ; ws2812_ctrl ; work ;
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; |sld_hub:auto_hub| ; 149 (1) ; 91 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 58 (1) ; 21 (0) ; 70 (0) ; |stark_machine|sld_hub:auto_hub ; sld_hub ; altera_sld ;
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; |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 148 (0) ; 91 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (0) ; 21 (0) ; 70 (0) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric ; alt_sld_fab_with_jtag_input ; altera_sld ;
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; |alt_sld_fab:instrumentation_fabric| ; 148 (0) ; 91 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (0) ; 21 (0) ; 70 (0) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab:alt_sld_fab| ; 148 (6) ; 91 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 57 (1) ; 21 (0) ; 70 (0) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; alt_sld_fab_alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric| ; 147 (0) ; 86 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 56 (0) ; 21 (0) ; 70 (0) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab ;
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; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub| ; 147 (106) ; 86 (58) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 56 (43) ; 21 (20) ; 70 (44) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; sld_jtag_hub ; work ;
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; |sld_rom_sr:hub_info_reg| ; 21 (21) ; 9 (9) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 12 (12) ; 0 (0) ; 9 (9) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ; sld_rom_sr ; work ;
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; |sld_shadow_jsm:shadow_jsm| ; 20 (20) ; 19 (19) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 18 (18) ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm ; altera_sld ;
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; |sld_signaltap:auto_signaltap_0| ; 1077 (102) ; 950 (100) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 127 (2) ; 561 (100) ; 389 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0 ; sld_signaltap ; work ;
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; |sld_signaltap_impl:sld_signaltap_body| ; 975 (0) ; 850 (0) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 125 (0) ; 461 (0) ; 389 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; sld_signaltap_impl ; work ;
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; |sld_signaltap_implb:sld_signaltap_body| ; 975 (311) ; 850 (282) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 125 (33) ; 461 (224) ; 389 (56) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body ; sld_signaltap_implb ; work ;
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; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 72 (70) ; 70 (70) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 47 (47) ; 24 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; altdpram ; work ;
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; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (0) ; 0 (0) ; 1 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; lpm_decode ; work ;
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; |decode_dvf:auto_generated| ; 2 (2) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 1 (1) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_dvf:auto_generated ; decode_dvf ; work ;
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; |lpm_mux:mux| ; 23 (0) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; lpm_mux ; work ;
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; |mux_rsc:auto_generated| ; 23 (23) ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 23 (23) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_rsc:auto_generated ; mux_rsc ; work ;
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; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; altsyncram ; work ;
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; |altsyncram_sa24:auto_generated| ; 0 (0) ; 0 (0) ; 0 (0) ; 102400 ; 13 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_sa24:auto_generated ; altsyncram_sa24 ; work ;
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; |lpm_shiftreg:segment_offset_config_deserialize| ; 11 (11) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 11 (11) ; 0 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; lpm_shiftreg ; work ;
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; |lpm_shiftreg:status_register| ; 17 (17) ; 17 (17) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 17 (17) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register ; lpm_shiftreg ; work ;
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; |serial_crc_16:\tdo_crc_gen:tdo_crc_calc| ; 14 (14) ; 13 (13) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 13 (13) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc ; serial_crc_16 ; work ;
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; |sld_buffer_manager:sld_buffer_manager_inst| ; 103 (103) ; 64 (64) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 35 (35) ; 15 (15) ; 53 (53) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; sld_buffer_manager ; work ;
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; |sld_ela_control:ela_control| ; 282 (1) ; 266 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (0) ; 164 (0) ; 102 (1) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control ; sld_ela_control ; work ;
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; |lpm_shiftreg:trigger_config_deserialize| ; 4 (4) ; 4 (4) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; lpm_shiftreg ; work ;
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; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 250 (0) ; 250 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 150 (0) ; 100 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; sld_ela_basic_multi_level_trigger ; work ;
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; |lpm_shiftreg:trigger_condition_deserialize| ; 150 (150) ; 150 (150) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 149 (149) ; 1 (1) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; lpm_shiftreg ; work ;
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; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 101 (0) ; 100 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (0) ; 100 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; sld_mbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 3 (3) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 2 (2) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; sld_sbpmg ; work ;
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; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 27 (17) ; 11 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 16 (16) ; 10 (0) ; 1 (1) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; sld_ela_trigger_flow_mgr ; work ;
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; |lpm_shiftreg:trigger_config_deserialize| ; 10 (10) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 10 (10) ; 0 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; lpm_shiftreg ; work ;
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; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 137 (10) ; 119 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 17 (10) ; 0 (0) ; 120 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; sld_offload_buffer_mgr ; work ;
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; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 8 (0) ; 6 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 6 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; lpm_counter ; work ;
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; |cntr_fgi:auto_generated| ; 8 (8) ; 6 (6) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 6 (6) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_fgi:auto_generated ; cntr_fgi ; work ;
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; |lpm_counter:read_pointer_counter| ; 11 (0) ; 11 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; lpm_counter ; work ;
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; |cntr_g9j:auto_generated| ; 11 (11) ; 11 (11) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 11 (11) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_g9j:auto_generated ; cntr_g9j ; work ;
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; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 5 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; lpm_counter ; work ;
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; |cntr_egi:auto_generated| ; 7 (7) ; 5 (5) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 5 (5) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_egi:auto_generated ; cntr_egi ; work ;
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; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 1 (0) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; lpm_counter ; work ;
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; |cntr_23j:auto_generated| ; 3 (3) ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 1 (1) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_23j:auto_generated ; cntr_23j ; work ;
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; |lpm_shiftreg:info_data_shift_out| ; 24 (24) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 24 (24) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; lpm_shiftreg ; work ;
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; |lpm_shiftreg:ram_data_shift_out| ; 50 (50) ; 50 (50) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 50 (50) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; lpm_shiftreg ; work ;
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; |lpm_shiftreg:status_data_shift_out| ; 24 (24) ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 23 (23) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; lpm_shiftreg ; work ;
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; |sld_rom_sr:crc_rom_sr| ; 30 (30) ; 8 (8) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 0 (0) ; 8 (8) ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; sld_rom_sr ; work ;
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; |uart_rx:uart_rx_inst| ; 50 (50) ; 28 (28) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 22 (22) ; 1 (1) ; 27 (27) ; |stark_machine|uart_rx:uart_rx_inst ; uart_rx ; work ;
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; |uart_tx:uart_tx_inst| ; 40 (40) ; 27 (27) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 4 (4) ; 23 (23) ; |stark_machine|uart_tx:uart_tx_inst ; uart_tx ; work ;
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+-----------------------------------------------------------------------------------------------------------------------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
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Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
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+--------------------------------------------------------------------------------------------+
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; Delay Chain Summary ;
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+------------+----------+---------------+---------------+-----------------------+-----+------+
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; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; TCOE ;
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+------------+----------+---------------+---------------+-----------------------+-----+------+
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; tx ; Output ; -- ; -- ; -- ; -- ; -- ;
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; led[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; led[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; led[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; led[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; beep ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[6] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; seg_led[7] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[0] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[1] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[2] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[3] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[4] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sel_led[5] ; Output ; -- ; -- ; -- ; -- ; -- ;
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; dout ; Output ; -- ; -- ; -- ; -- ; -- ;
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; sys_clk ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
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; sys_rst_n ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
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; rx ; Input ; (0) 0 ps ; -- ; -- ; -- ; -- ;
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+------------+----------+---------------+---------------+-----------------------+-----+------+
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+---------------------------------------------------+
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; Pad To Core Delay Chain Fanout ;
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+---------------------+-------------------+---------+
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; Source Pin / Fanout ; Pad To Core Index ; Setting ;
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+---------------------+-------------------+---------+
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; sys_clk ; ; ;
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; sys_rst_n ; ; ;
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; rx ; ; ;
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+---------------------+-------------------+---------+
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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Control Signals ;
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
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; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
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; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y12_N0 ; 510 ; Clock ; yes ; Global Clock ; GCLK1 ; -- ;
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; altera_internal_jtag~TMSUTAP ; JTAG_X1_Y12_N0 ; 23 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|WideNor0 ; LCCOMB_X23_Y14_N28 ; 1 ; Latch enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_300[23]~26 ; LCCOMB_X28_Y19_N4 ; 24 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_freq[6]~45 ; LCCOMB_X28_Y19_N24 ; 40 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_freq~44 ; LCCOMB_X30_Y22_N12 ; 16 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_note[0]~11 ; LCCOMB_X28_Y19_N30 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_note~10 ; LCCOMB_X28_Y19_N20 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_day[4]~19 ; LCCOMB_X14_Y20_N14 ; 17 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_day[4]~20 ; LCCOMB_X14_Y20_N8 ; 45 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_s[12]~32 ; LCCOMB_X19_Y18_N2 ; 28 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|cnt_fps[0]~20 ; LCCOMB_X19_Y18_N6 ; 10 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|cnt_fps[0]~21 ; LCCOMB_X19_Y18_N8 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[0]~2 ; LCCOMB_X22_Y16_N8 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[0]~9 ; LCCOMB_X22_Y16_N14 ; 2 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst|flag ; FF_X25_Y15_N11 ; 31 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst|led[0]~2 ; LCCOMB_X25_Y15_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|bit_num[2]~14 ; LCCOMB_X28_Y16_N8 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|bit_num[2]~7 ; LCCOMB_X28_Y16_N14 ; 12 ; Clock enable, Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_0[5]~10 ; LCCOMB_X28_Y19_N2 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_0[5]~8 ; LCCOMB_X26_Y17_N2 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_1[0]~15 ; LCCOMB_X24_Y17_N8 ; 6 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_1[0]~22 ; LCCOMB_X24_Y17_N28 ; 6 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_rst[9]~28 ; LCCOMB_X24_Y17_N2 ; 26 ; Sync. clear ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_rst[9]~29 ; LCCOMB_X28_Y16_N12 ; 26 ; Clock enable ; no ; -- ; -- ; -- ;
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; circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|led_num[2]~15 ; LCCOMB_X28_Y16_N4 ; 7 ; Sync. clear ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|clr_reg ; FF_X14_Y10_N1 ; 27 ; Async. clear ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|design_hash_proc~0 ; LCCOMB_X12_Y11_N10 ; 4 ; Sync. load ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_info_reg_ena ; LCCOMB_X12_Y11_N12 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|hub_info_reg_ena~0 ; LCCOMB_X10_Y11_N18 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|identity_contrib_shift_reg[0]~1 ; LCCOMB_X13_Y12_N28 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][0]~0 ; LCCOMB_X14_Y11_N2 ; 10 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][4] ; FF_X13_Y11_N1 ; 18 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irf_reg[1][7] ; FF_X13_Y11_N31 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|irsr_reg[2]~2 ; LCCOMB_X13_Y11_N24 ; 9 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]~15 ; LCCOMB_X12_Y12_N28 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|mixer_addr_reg_internal[4]~16 ; LCCOMB_X12_Y11_N8 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|reset_ena_reg_proc~0 ; LCCOMB_X11_Y11_N24 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|WORD_SR[1]~17 ; LCCOMB_X12_Y11_N14 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0]~13 ; LCCOMB_X16_Y11_N26 ; 5 ; Sync. clear ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg|word_counter[0]~20 ; LCCOMB_X12_Y11_N20 ; 5 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[0] ; FF_X14_Y10_N27 ; 15 ; Async. clear ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[11] ; FF_X14_Y10_N3 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[3] ; FF_X14_Y10_N31 ; 36 ; Sync. load ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm|state[4] ; FF_X11_Y11_N17 ; 33 ; Sync. load ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_dr_scan_proc~0 ; LCCOMB_X14_Y10_N18 ; 3 ; Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|virtual_ir_scan_reg ; FF_X21_Y10_N25 ; 35 ; Async. clear, Clock enable ; no ; -- ; -- ; -- ;
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; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|sldfabric_ident_writedata[0]~0 ; LCCOMB_X13_Y12_N22 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_dvf:auto_generated|eq_node[0]~1 ; LCCOMB_X6_Y10_N28 ; 23 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_dvf:auto_generated|eq_node[1]~0 ; LCCOMB_X6_Y10_N6 ; 23 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|buffer_write_enable_delayed ; FF_X10_Y10_N29 ; 16 ; Clock enable, Write enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|collect_data ; LCCOMB_X10_Y10_N2 ; 29 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~0 ; LCCOMB_X11_Y10_N28 ; 32 ; Sync. clear ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|process_0~1 ; LCCOMB_X10_Y11_N30 ; 32 ; Sync. load ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all ; FF_X8_Y11_N27 ; 327 ; Async. clear ; yes ; Global Clock ; GCLK3 ; -- ;
|
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc|lfsr[10]~1 ; LCCOMB_X7_Y11_N8 ; 13 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|final_trigger_set~4 ; LCCOMB_X10_Y10_N4 ; 24 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0 ; LCCOMB_X10_Y10_N18 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|Equal2~1 ; LCCOMB_X18_Y9_N0 ; 1 ; Clock enable ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset ; LCCOMB_X16_Y10_N30 ; 12 ; Sync. load ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_fgi:auto_generated|counter_reg_bit[5]~0 ; LCCOMB_X17_Y9_N26 ; 6 ; Sync. load ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_egi:auto_generated|counter_reg_bit[4]~0 ; LCCOMB_X18_Y9_N28 ; 5 ; Sync. load ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_23j:auto_generated|counter_reg_bit[0]~0 ; LCCOMB_X16_Y10_N2 ; 1 ; Sync. load ; no ; -- ; -- ; -- ;
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|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|read_pointer_counter_clk_ena ; LCCOMB_X17_Y9_N20 ; 11 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]~8 ; LCCOMB_X18_Y11_N20 ; 4 ; Sync. clear ; no ; -- ; -- ; -- ;
|
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|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|WORD_SR[1]~9 ; LCCOMB_X18_Y11_N26 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
|
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr|word_counter[2]~5 ; LCCOMB_X18_Y11_N16 ; 4 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|status_shift_enable~1 ; LCCOMB_X10_Y9_N26 ; 17 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_len_reg[12]~34 ; LCCOMB_X7_Y11_N10 ; 32 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|tdo_crc_val_shift_reg[0]~1 ; LCCOMB_X11_Y10_N0 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|trigger_setup_ena ; LCCOMB_X11_Y10_N22 ; 175 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
|
; sys_clk ; PIN_E1 ; 836 ; Clock ; yes ; Global Clock ; GCLK2 ; -- ;
|
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|
|
|
; sys_rst_n ; PIN_E15 ; 263 ; Async. clear ; yes ; Global Clock ; GCLK9 ; -- ;
|
|
|
|
|
|
; uart_rx:uart_rx_inst|add_cnt_bit ; LCCOMB_X23_Y8_N22 ; 7 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
|
|
|
; uart_rx:uart_rx_inst|rx_flag ; FF_X23_Y8_N31 ; 15 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
|
|
|
; uart_rx:uart_rx_inst|rx_vld ; LCCOMB_X22_Y10_N18 ; 36 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
|
|
|
; uart_tx:uart_tx_inst|add_cnt_bit~4 ; LCCOMB_X22_Y8_N28 ; 12 ; Clock enable ; no ; -- ; -- ; -- ;
|
|
|
|
|
|
; uart_tx:uart_tx_inst|tx_flag ; FF_X22_Y8_N11 ; 16 ; Clock enable ; no ; -- ; -- ; -- ;
|
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|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------+---------+----------------------------+--------+----------------------+------------------+---------------------------+
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
; Global & Other Fast Signals ;
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
; Name ; Location ; Fan-Out ; Fan-Out Using Intentional Clock Skew ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ;
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
|
|
|
|
|
; altera_internal_jtag~TCKUTAP ; JTAG_X1_Y12_N0 ; 510 ; 0 ; Global Clock ; GCLK1 ; -- ;
|
|
|
|
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all ; FF_X8_Y11_N27 ; 327 ; 0 ; Global Clock ; GCLK3 ; -- ;
|
|
|
|
|
|
; sys_clk ; PIN_E1 ; 836 ; 0 ; Global Clock ; GCLK2 ; -- ;
|
|
|
|
|
|
; sys_rst_n ; PIN_E15 ; 263 ; 0 ; Global Clock ; GCLK9 ; -- ;
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------+----------------+---------+--------------------------------------+----------------------+------------------+---------------------------+
|
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|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
; Fitter RAM Summary ;
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
|
|
|
|
|
|
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M9Ks ; MIF ; Location ; Mixed Width RDW Mode ; Port A RDW Mode ; Port B RDW Mode ; ECC Mode ; ECC Pipeline Registers ; Fits in MLABs ;
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
|
|
|
|
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_sa24:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Dual Clocks ; 2048 ; 50 ; 2048 ; 50 ; yes ; no ; yes ; no ; 102400 ; 2048 ; 50 ; 2048 ; 50 ; 102400 ; 13 ; None ; M9K_X15_Y12_N0, M9K_X15_Y13_N0, M9K_X15_Y15_N0, M9K_X15_Y14_N0, M9K_X15_Y9_N0, M9K_X27_Y11_N0, M9K_X27_Y14_N0, M9K_X15_Y11_N0, M9K_X27_Y9_N0, M9K_X27_Y10_N0, M9K_X27_Y13_N0, M9K_X27_Y12_N0, M9K_X15_Y10_N0 ; Don't care ; New data with NBE Read ; New data with NBE Read ; Off ; No ; No - Unknown ;
|
|
|
|
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+-------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+--------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+------+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------------+------------------------+------------------------+----------+------------------------+---------------+
|
|
|
|
|
|
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-------------------------------------------------+
|
|
|
|
|
|
; Routing Usage Summary ;
|
|
|
|
|
|
+-----------------------+-------------------------+
|
|
|
|
|
|
; Routing Resource Type ; Usage ;
|
|
|
|
|
|
+-----------------------+-------------------------+
|
|
|
|
|
|
; Block interconnects ; 2,614 / 32,401 ( 8 % ) ;
|
|
|
|
|
|
; C16 interconnects ; 2 / 1,326 ( < 1 % ) ;
|
|
|
|
|
|
; C4 interconnects ; 1,089 / 21,816 ( 5 % ) ;
|
|
|
|
|
|
; Direct links ; 618 / 32,401 ( 2 % ) ;
|
|
|
|
|
|
; Global clocks ; 4 / 10 ( 40 % ) ;
|
|
|
|
|
|
; Local interconnects ; 1,600 / 10,320 ( 16 % ) ;
|
|
|
|
|
|
; R24 interconnects ; 20 / 1,289 ( 2 % ) ;
|
|
|
|
|
|
; R4 interconnects ; 1,289 / 28,186 ( 5 % ) ;
|
|
|
|
|
|
+-----------------------+-------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
|
|
|
; LAB Logic Elements ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
; Number of Logic Elements (Average = 12.23) ; Number of LABs (Total = 222) ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
; 1 ; 10 ;
|
|
|
|
|
|
; 2 ; 6 ;
|
|
|
|
|
|
; 3 ; 3 ;
|
|
|
|
|
|
; 4 ; 5 ;
|
|
|
|
|
|
; 5 ; 10 ;
|
|
|
|
|
|
; 6 ; 7 ;
|
|
|
|
|
|
; 7 ; 4 ;
|
|
|
|
|
|
; 8 ; 4 ;
|
|
|
|
|
|
; 9 ; 2 ;
|
|
|
|
|
|
; 10 ; 10 ;
|
|
|
|
|
|
; 11 ; 9 ;
|
|
|
|
|
|
; 12 ; 9 ;
|
|
|
|
|
|
; 13 ; 14 ;
|
|
|
|
|
|
; 14 ; 17 ;
|
|
|
|
|
|
; 15 ; 25 ;
|
|
|
|
|
|
; 16 ; 87 ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+--------------------------------------------------------------------+
|
|
|
|
|
|
; LAB-wide Signals ;
|
|
|
|
|
|
+------------------------------------+-------------------------------+
|
|
|
|
|
|
; LAB-wide Signals (Average = 1.43) ; Number of LABs (Total = 222) ;
|
|
|
|
|
|
+------------------------------------+-------------------------------+
|
|
|
|
|
|
; 1 Async. clear ; 83 ;
|
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|
|
; 1 Clock ; 110 ;
|
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|
|
; 1 Clock enable ; 75 ;
|
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|
|
; 1 Sync. clear ; 12 ;
|
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|
; 1 Sync. load ; 4 ;
|
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|
|
; 2 Clock enables ; 3 ;
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|
; 2 Clocks ; 30 ;
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|
|
+------------------------------------+-------------------------------+
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|
|
+------------------------------------------------------------------------------+
|
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|
|
; LAB Signals Sourced ;
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|
|
|
|
+----------------------------------------------+-------------------------------+
|
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|
|
|
; Number of Signals Sourced (Average = 17.15) ; Number of LABs (Total = 222) ;
|
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|
|
|
+----------------------------------------------+-------------------------------+
|
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|
|
; 0 ; 1 ;
|
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|
|
; 1 ; 4 ;
|
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|
|
; 2 ; 9 ;
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|
|
; 3 ; 0 ;
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|
|
; 4 ; 7 ;
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|
|
; 5 ; 3 ;
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|
|
; 6 ; 4 ;
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|
|
; 7 ; 6 ;
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|
|
; 8 ; 3 ;
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|
|
; 9 ; 1 ;
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|
|
; 10 ; 5 ;
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|
|
; 11 ; 4 ;
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|
|
; 12 ; 10 ;
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|
|
; 13 ; 8 ;
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|
|
; 14 ; 10 ;
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|
|
; 15 ; 32 ;
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|
|
; 16 ; 14 ;
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|
|
; 17 ; 6 ;
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|
|
; 18 ; 4 ;
|
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|
|
|
; 19 ; 2 ;
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|
|
; 20 ; 7 ;
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|
|
; 21 ; 8 ;
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|
|
; 22 ; 11 ;
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|
|
; 23 ; 8 ;
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|
|
; 24 ; 8 ;
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|
|
; 25 ; 5 ;
|
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|
|
|
; 26 ; 4 ;
|
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|
|
|
; 27 ; 7 ;
|
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|
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|
|
; 28 ; 8 ;
|
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|
|
|
|
; 29 ; 7 ;
|
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|
|
|
|
; 30 ; 6 ;
|
|
|
|
|
|
; 31 ; 2 ;
|
|
|
|
|
|
; 32 ; 8 ;
|
|
|
|
|
|
+----------------------------------------------+-------------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------------------+
|
|
|
|
|
|
; LAB Signals Sourced Out ;
|
|
|
|
|
|
+-------------------------------------------------+-------------------------------+
|
|
|
|
|
|
; Number of Signals Sourced Out (Average = 6.12) ; Number of LABs (Total = 222) ;
|
|
|
|
|
|
+-------------------------------------------------+-------------------------------+
|
|
|
|
|
|
; 0 ; 1 ;
|
|
|
|
|
|
; 1 ; 26 ;
|
|
|
|
|
|
; 2 ; 37 ;
|
|
|
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|
|
; 3 ; 25 ;
|
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|
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|
|
; 4 ; 16 ;
|
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|
|
|
|
; 5 ; 17 ;
|
|
|
|
|
|
; 6 ; 10 ;
|
|
|
|
|
|
; 7 ; 12 ;
|
|
|
|
|
|
; 8 ; 16 ;
|
|
|
|
|
|
; 9 ; 12 ;
|
|
|
|
|
|
; 10 ; 11 ;
|
|
|
|
|
|
; 11 ; 7 ;
|
|
|
|
|
|
; 12 ; 10 ;
|
|
|
|
|
|
; 13 ; 4 ;
|
|
|
|
|
|
; 14 ; 5 ;
|
|
|
|
|
|
; 15 ; 3 ;
|
|
|
|
|
|
; 16 ; 6 ;
|
|
|
|
|
|
; 17 ; 0 ;
|
|
|
|
|
|
; 18 ; 1 ;
|
|
|
|
|
|
; 19 ; 1 ;
|
|
|
|
|
|
; 20 ; 1 ;
|
|
|
|
|
|
; 21 ; 0 ;
|
|
|
|
|
|
; 22 ; 0 ;
|
|
|
|
|
|
; 23 ; 0 ;
|
|
|
|
|
|
; 24 ; 0 ;
|
|
|
|
|
|
; 25 ; 0 ;
|
|
|
|
|
|
; 26 ; 0 ;
|
|
|
|
|
|
; 27 ; 1 ;
|
|
|
|
|
|
+-------------------------------------------------+-------------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------+
|
|
|
|
|
|
; LAB Distinct Inputs ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
; Number of Distinct Inputs (Average = 9.77) ; Number of LABs (Total = 222) ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
; 0 ; 0 ;
|
|
|
|
|
|
; 1 ; 1 ;
|
|
|
|
|
|
; 2 ; 9 ;
|
|
|
|
|
|
; 3 ; 20 ;
|
|
|
|
|
|
; 4 ; 18 ;
|
|
|
|
|
|
; 5 ; 13 ;
|
|
|
|
|
|
; 6 ; 14 ;
|
|
|
|
|
|
; 7 ; 15 ;
|
|
|
|
|
|
; 8 ; 11 ;
|
|
|
|
|
|
; 9 ; 21 ;
|
|
|
|
|
|
; 10 ; 9 ;
|
|
|
|
|
|
; 11 ; 18 ;
|
|
|
|
|
|
; 12 ; 11 ;
|
|
|
|
|
|
; 13 ; 12 ;
|
|
|
|
|
|
; 14 ; 7 ;
|
|
|
|
|
|
; 15 ; 3 ;
|
|
|
|
|
|
; 16 ; 7 ;
|
|
|
|
|
|
; 17 ; 3 ;
|
|
|
|
|
|
; 18 ; 5 ;
|
|
|
|
|
|
; 19 ; 5 ;
|
|
|
|
|
|
; 20 ; 6 ;
|
|
|
|
|
|
; 21 ; 4 ;
|
|
|
|
|
|
; 22 ; 4 ;
|
|
|
|
|
|
; 23 ; 1 ;
|
|
|
|
|
|
; 24 ; 0 ;
|
|
|
|
|
|
; 25 ; 3 ;
|
|
|
|
|
|
; 26 ; 0 ;
|
|
|
|
|
|
; 27 ; 0 ;
|
|
|
|
|
|
; 28 ; 0 ;
|
|
|
|
|
|
; 29 ; 0 ;
|
|
|
|
|
|
; 30 ; 1 ;
|
|
|
|
|
|
+---------------------------------------------+-------------------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+------------------------------------------+
|
|
|
|
|
|
; I/O Rules Summary ;
|
|
|
|
|
|
+----------------------------------+-------+
|
|
|
|
|
|
; I/O Rules Statistic ; Total ;
|
|
|
|
|
|
+----------------------------------+-------+
|
|
|
|
|
|
; Total I/O Rules ; 30 ;
|
|
|
|
|
|
; Number of I/O Rules Passed ; 12 ;
|
|
|
|
|
|
; Number of I/O Rules Failed ; 0 ;
|
|
|
|
|
|
; Number of I/O Rules Unchecked ; 0 ;
|
|
|
|
|
|
; Number of I/O Rules Inapplicable ; 18 ;
|
|
|
|
|
|
+----------------------------------+-------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
; I/O Rules Details ;
|
|
|
|
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
|
|
|
|
|
; Status ; ID ; Category ; Rule Description ; Severity ; Information ; Area ; Extra Information ;
|
|
|
|
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
|
|
|
|
|
; Pass ; IO_000001 ; Capacity Checks ; Number of pins in an I/O bank should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000002 ; Capacity Checks ; Number of clocks in an I/O bank should not exceed the number of clocks available. ; Critical ; No Global Signal assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000003 ; Capacity Checks ; Number of pins in a Vrefgroup should not exceed the number of locations available. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000004 ; Voltage Compatibility Checks ; The I/O bank should support the requested VCCIO. ; Critical ; No IOBANK_VCCIO assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000005 ; Voltage Compatibility Checks ; The I/O bank should not have competing VREF values. ; Critical ; No VREF I/O Standard assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000006 ; Voltage Compatibility Checks ; The I/O bank should not have competing VCCIO values. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000007 ; Valid Location Checks ; Checks for unavailable locations. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000008 ; Valid Location Checks ; Checks for reserved locations. ; Critical ; No reserved LogicLock region found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000009 ; I/O Properties Checks for One I/O ; The location should support the requested I/O standard. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000010 ; I/O Properties Checks for One I/O ; The location should support the requested I/O direction. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000011 ; I/O Properties Checks for One I/O ; The location should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000012 ; I/O Properties Checks for One I/O ; The location should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000013 ; I/O Properties Checks for One I/O ; The location should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000014 ; I/O Properties Checks for One I/O ; The location should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000015 ; I/O Properties Checks for One I/O ; The location should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000018 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Current Strength. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000019 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000020 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested PCI Clamp Diode. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000021 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Weak Pull Up value. ; Critical ; No Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000022 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Bus Hold value. ; Critical ; No Enable Bus-Hold Circuitry assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000023 ; I/O Properties Checks for One I/O ; The I/O standard should support the Open Drain value. ; Critical ; No open drain assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000024 ; I/O Properties Checks for One I/O ; The I/O direction should support the On Chip Termination value. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000026 ; I/O Properties Checks for One I/O ; On Chip Termination and Current Strength should not be used at the same time. ; Critical ; No Current Strength assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000027 ; I/O Properties Checks for One I/O ; Weak Pull Up and Bus Hold should not be used at the same time. ; Critical ; No Enable Bus-Hold Circuitry or Weak Pull-Up Resistor assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000045 ; I/O Properties Checks for One I/O ; The I/O standard should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000046 ; I/O Properties Checks for One I/O ; The location should support the requested Slew Rate value. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000047 ; I/O Properties Checks for One I/O ; On Chip Termination and Slew Rate should not be used at the same time. ; Critical ; No Slew Rate assignments found. ; I/O ; ;
|
|
|
|
|
|
; Pass ; IO_000033 ; Electromigration Checks ; Current density for consecutive I/Os should not exceed 240mA for row I/Os and 240mA for column I/Os. ; Critical ; 0 such failures found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000034 ; SI Related Distance Checks ; Single-ended outputs should be 5 LAB row(s) away from a differential I/O. ; High ; No Differential I/O Standard assignments found. ; I/O ; ;
|
|
|
|
|
|
; Inapplicable ; IO_000042 ; SI Related SSO Limit Checks ; No more than 20 outputs are allowed in a VREF group when VREF is being read from. ; High ; No VREF I/O Standard assignments found. ; I/O ; ;
|
|
|
|
|
|
; ---- ; ---- ; Disclaimer ; OCT rules are checked but not reported. ; None ; ---- ; On Chip Termination ; ;
|
|
|
|
|
|
+--------------+-----------+-----------------------------------+------------------------------------------------------------------------------------------------------+----------+--------------------------------------------------------------------------+---------------------+-------------------+
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
|
|
|
|
|
; I/O Rules Matrix ;
|
|
|
|
|
|
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
|
|
|
|
|
; Pin/Rules ; IO_000001 ; IO_000002 ; IO_000003 ; IO_000004 ; IO_000005 ; IO_000006 ; IO_000007 ; IO_000008 ; IO_000009 ; IO_000010 ; IO_000011 ; IO_000012 ; IO_000013 ; IO_000014 ; IO_000015 ; IO_000018 ; IO_000019 ; IO_000020 ; IO_000021 ; IO_000022 ; IO_000023 ; IO_000024 ; IO_000026 ; IO_000027 ; IO_000045 ; IO_000046 ; IO_000047 ; IO_000033 ; IO_000034 ; IO_000042 ;
|
|
|
|
|
|
+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
|
|
|
|
|
|
; Total Pass ; 24 ; 0 ; 24 ; 0 ; 0 ; 28 ; 24 ; 0 ; 28 ; 28 ; 0 ; 21 ; 0 ; 0 ; 3 ; 0 ; 21 ; 3 ; 0 ; 0 ; 0 ; 21 ; 0 ; 0 ; 0 ; 0 ; 0 ; 28 ; 0 ; 0 ;
|
|
|
|
|
|
; Total Unchecked ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
|
|
|
|
; Total Inapplicable ; 4 ; 28 ; 4 ; 28 ; 28 ; 0 ; 4 ; 28 ; 0 ; 0 ; 28 ; 7 ; 28 ; 28 ; 25 ; 28 ; 7 ; 25 ; 28 ; 28 ; 28 ; 7 ; 28 ; 28 ; 28 ; 28 ; 28 ; 0 ; 28 ; 28 ;
|
|
|
|
|
|
; Total Fail ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
|
|
|
|
|
|
; tx ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; led[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; led[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; led[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; led[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; beep ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
|
|
; seg_led[6] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
|
|
|
|
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|
; seg_led[7] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[0] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[1] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[2] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[3] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[4] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sel_led[5] ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; dout ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sys_clk ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; sys_rst_n ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; rx ; Pass ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; altera_reserved_tms ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; altera_reserved_tck ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; altera_reserved_tdi ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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; altera_reserved_tdo ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ; Pass ; Pass ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Inapplicable ; Pass ; Inapplicable ; Inapplicable ;
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+---------------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+-----------+-----------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+--------------+-----------+--------------+--------------+
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+---------------------------------------------------------------------------------------------+
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; Fitter Device Options ;
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+------------------------------------------------------------------+--------------------------+
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; Option ; Setting ;
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+------------------------------------------------------------------+--------------------------+
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; Enable user-supplied start-up clock (CLKUSR) ; Off ;
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; Enable device-wide reset (DEV_CLRn) ; Off ;
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; Enable device-wide output enable (DEV_OE) ; Off ;
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; Enable INIT_DONE output ; Off ;
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; Configuration scheme ; Active Serial ;
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; Error detection CRC ; Off ;
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; Enable open drain on CRC_ERROR pin ; Off ;
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; Enable input tri-state on active configuration pins in user mode ; Off ;
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; Configuration Voltage Level ; Auto ;
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; Force Configuration Voltage Level ; Off ;
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; nCEO ; Unreserved ;
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; Data[0] ; As input tri-stated ;
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; Data[1]/ASDO ; As input tri-stated ;
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; Data[7..2] ; Unreserved ;
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; FLASH_nCE/nCSO ; As input tri-stated ;
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; Other Active Parallel pins ; Unreserved ;
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; DCLK ; As output driving ground ;
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+------------------------------------------------------------------+--------------------------+
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+------------------------------------+
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; Operating Settings and Conditions ;
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+---------------------------+--------+
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; Setting ; Value ;
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+---------------------------+--------+
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; Nominal Core Voltage ; 1.20 V ;
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; Low Junction Temperature ; 0 <20>C ;
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; High Junction Temperature ; 85 <20>C ;
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+---------------------------+--------+
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+-----------------+
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; Fitter Messages ;
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+-----------------+
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Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
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Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
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Info (119006): Selected device EP4CE6F17C8 for design "agi_fpga"
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Info (21077): Low junction temperature is 0 degrees C
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Info (21077): High junction temperature is 85 degrees C
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Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
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Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature.
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Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices
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Info (176445): Device EP4CE10F17C8 is compatible
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Info (176445): Device EP4CE15F17C8 is compatible
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Info (176445): Device EP4CE22F17C8 is compatible
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Info (169124): Fitter converted 4 user pins into dedicated programming pins
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Info (169125): Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1
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Info (169125): Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2
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Info (169125): Pin ~ALTERA_DCLK~ is reserved at location H1
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Info (169125): Pin ~ALTERA_DATA0~ is reserved at location H2
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Warning (15714): Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details
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Info (176045): Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
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Warning (335093): The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the "User-Specified and Inferred Latches" table in the Analysis & Synthesis report.
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Info (332164): Evaluating HDL-embedded SDC commands
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Info (332165): Entity sld_hub
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Info (332166): create_clock -name altera_reserved_tck [get_ports {altera_reserved_tck}] -period 10MHz
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Info (332166): set_clock_groups -asynchronous -group {altera_reserved_tck}
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Critical Warning (332012): Synopsys Design Constraints File file not found: 'agi_fpga.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
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Warning (332060): Node: sys_clk was determined to be a clock but was found without an associated clock assignment.
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Info (13166): Register circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_day[0] is being clocked by sys_clk
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Warning (332060): Node: byte_num[0] was determined to be a clock but was found without an associated clock assignment.
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Info (13166): Latch circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[1] is being clocked by byte_num[0]
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Critical Warning (332168): The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command.
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Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)
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Critical Warning (332169): From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)
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Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements
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Info (332111): Found 1 clocks
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Info (332111): Period Clock Name
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Info (332111): ======== ============
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Info (332111): 100.000 altera_reserved_tck
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Info (176353): Automatically promoted node sys_clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 2
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2
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Info (176353): Automatically promoted node altera_internal_jtag~TCKUTAP
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
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Info (176353): Automatically promoted node sys_rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p)) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 3
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9
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Info (176353): Automatically promoted node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|reset_all File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd Line: 882
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Info (176355): Automatically promoted destinations to use location or clock signal Global Clock
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Info (176356): Following destination nodes may be non-global or may not use global or regional clocks
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Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|last_buffer_write_address_sig[0]~0 File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 356
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Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset~0 File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 638
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Info (176357): Destination node sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|acq_buf_read_reset File: d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd Line: 638
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Info (176233): Starting register packing
|
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Info (176235): Finished register packing
|
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Extra Info (176219): No registers were packed into other blocks
|
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Info (171121): Fitter preparation operations ending: elapsed time is 00:00:02
|
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Info (14896): Fitter has disabled Advanced Physical Optimization because it is not supported for the current family.
|
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Info (170189): Fitter placement preparation operations beginning
|
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Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:01
|
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Info (170191): Fitter placement operations beginning
|
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Info (170137): Fitter placement was successful
|
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Info (170192): Fitter placement operations ending: elapsed time is 00:00:01
|
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Info (170193): Fitter routing operations beginning
|
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Info (170195): Router estimated average interconnect usage is 4% of the available device resources
|
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Info (170196): Router estimated peak interconnect usage is 8% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24
|
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Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
|
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Info (170201): Optimizations that may affect the design's routability were skipped
|
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Info (170200): Optimizations that may affect the design's timing were skipped
|
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Info (170194): Fitter routing operations ending: elapsed time is 00:00:01
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Info (11888): Total time spent on timing analysis during the Fitter is 0.52 seconds.
|
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Info (334003): Started post-fitting delay annotation
|
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Info (334004): Delay annotation completed successfully
|
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Info (334003): Started post-fitting delay annotation
|
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|
Info (334004): Delay annotation completed successfully
|
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|
|
Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:02
|
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|
|
Warning (292000): FLEXlm software error: Invalid (inconsistent) license key. The license key and data for the feature do not match. This usually happens when a license file has been altered. Feature: quartus_seu_mitigation License path: D:\intelFPGA_lite\license.dat; FlexNet Licensing error:-8,523 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com"..
|
|
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|
|
|
Warning (292000): FLEXlm software error: Invalid (inconsistent) license key. The license key and data for the feature do not match. This usually happens when a license file has been altered. Feature: quartus_seu_mitigation License path: D:\intelFPGA_lite\license.dat; FlexNet Licensing error:-8,523 For further information, refer to the FlexNet Licensing documentation, available at "www.flexerasoftware.com"..
|
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|
Info (144001): Generated suppressed messages file C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.fit.smsg
|
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Info: Quartus Prime Fitter was successful. 0 errors, 12 warnings
|
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|
Info: Peak virtual memory: 5519 megabytes
|
|
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|
|
Info: Processing ended: Thu Jun 20 16:28:35 2024
|
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|
|
Info: Elapsed time: 00:00:15
|
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|
|
Info: Total CPU time (on all processors): 00:00:07
|
|
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|
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+----------------------------+
|
|
|
|
|
|
; Fitter Suppressed Messages ;
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|
|
|
|
+----------------------------+
|
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|
|
The suppressed messages can be found in C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.fit.smsg.
|
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