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167 lines
21 KiB
Plaintext
167 lines
21 KiB
Plaintext
5 months ago
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Flow report for agi_fpga
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Thu Jun 20 16:28:50 2024
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Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Flow Summary
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3. Flow Settings
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4. Flow Non-Default Global Settings
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5. Flow Elapsed Time
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6. Flow OS Summary
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7. Flow Log
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8. Flow Messages
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9. Flow Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------------+
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; Flow Summary ;
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+------------------------------------+---------------------------------------------+
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; Flow Status ; Successful - Thu Jun 20 16:28:50 2024 ;
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; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
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; Revision Name ; agi_fpga ;
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; Top-level Entity Name ; stark_machine ;
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; Family ; Cyclone IV E ;
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; Device ; EP4CE6F17C8 ;
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; Timing Models ; Final ;
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; Total logic elements ; 2,715 / 6,272 ( 43 % ) ;
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; Total combinational functions ; 2,124 / 6,272 ( 34 % ) ;
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; Dedicated logic registers ; 1,320 / 6,272 ( 21 % ) ;
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; Total registers ; 1320 ;
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; Total pins ; 24 / 180 ( 13 % ) ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 102,400 / 276,480 ( 37 % ) ;
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; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ;
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; Total PLLs ; 0 / 2 ( 0 % ) ;
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+------------------------------------+---------------------------------------------+
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+-----------------------------------------+
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; Flow Settings ;
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+-------------------+---------------------+
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; Option ; Setting ;
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+-------------------+---------------------+
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; Start date & time ; 06/20/2024 16:27:14 ;
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; Main task ; Compilation ;
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; Revision Name ; agi_fpga ;
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+-------------------+---------------------+
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Flow Non-Default Global Settings ;
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+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+
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; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
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+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+
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; COMPILER_SIGNATURE_ID ; 118933435750018.171887203417796 ; -- ; -- ; -- ;
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; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ;
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; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; <None> ; -- ; -- ;
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; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ;
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; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ;
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; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
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; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
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; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ;
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; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
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; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ;
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; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
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; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ;
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; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ;
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; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ;
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; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ;
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; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ;
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; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ;
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; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ;
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; SLD_FILE ; db/stp1_auto_stripped.stp ; -- ; -- ; -- ;
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; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_RAM_BLOCK_TYPE=AUTO ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=50 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=50 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_BITS=50 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=805334528 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=175 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SEGMENT_SIZE=2048 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ATTRIBUTE_MEM_MODE=OFF ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_FLOW_USE_GENERATED=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_BITS=11 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_BUFFER_FULL_STOP=1 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_CURRENT_RESOURCE_WIDTH=1 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INCREMENTAL_ROUTING=1 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=2048 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_RAM_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_COUNTER_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ;
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; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ;
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; TOP_LEVEL_ENTITY ; stark_machine ; agi_fpga ; -- ; -- ;
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; USE_SIGNALTAP_FILE ; output_files/stp1.stp ; -- ; -- ; -- ;
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+-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+
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+--------------------------------------------------------------------------------------------------------------------------+
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; Flow Elapsed Time ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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; Analysis & Synthesis ; 00:01:03 ; 1.0 ; 4860 MB ; 00:01:29 ;
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; Fitter ; 00:00:13 ; 1.1 ; 5519 MB ; 00:00:06 ;
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; Assembler ; 00:00:02 ; 1.0 ; 4680 MB ; 00:00:01 ;
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; Timing Analyzer ; 00:00:04 ; 1.3 ; 4779 MB ; 00:00:02 ;
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; EDA Netlist Writer ; 00:00:05 ; 1.0 ; 4675 MB ; 00:00:03 ;
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; Total ; 00:01:27 ; -- ; -- ; 00:01:41 ;
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+----------------------+--------------+-------------------------+---------------------+------------------------------------+
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+------------------------------------------------------------------------------------+
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; Flow OS Summary ;
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+----------------------+------------------+------------+------------+----------------+
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; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
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+----------------------+------------------+------------+------------+----------------+
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; Analysis & Synthesis ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ;
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; Fitter ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ;
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; Assembler ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ;
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; Timing Analyzer ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ;
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; EDA Netlist Writer ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ;
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+----------------------+------------------+------------+------------+----------------+
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------------
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; Flow Log ;
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------------
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quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga
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quartus_fit --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga
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quartus_asm --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga
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quartus_sta agi_fpga -c agi_fpga
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quartus_eda --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga
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