agi_fpga/hardware/rtl/beep/pwm_beep.v

module pwm_beep(
    input   wire    sys_clk     ,
    input   wire    sys_rst_n   ,
    input   wire    pwm         ,

    output  reg     beep
);
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        beep <= 1'b1;
    end 
    else if(pwm)begin
        beep <= 1'b0;
    end
    else begin
        beep <= 1'b1;
    end  
end 
endmodule