agi_fpga/hardware/rtl/led/led_circuit.v

module led_circuit(
    input                   sys_clk     ,
    input                   sys_rst_n   ,
    input       [3: 0]      opcode      ,
    input       [3: 0]      data        ,
    input       [1: 0]      dev_id      ,//设备地址
    
    output reg  [3: 0]      led
);
parameter MAX = 28'd50_000_000;
reg [27: 0] cnt_1s;
wire        end_cnt;
wire        add_cnt;
reg         flag   ;
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag <= 1'b0;
    end 
    else if((dev_id == 2'd0) && (opcode == 4'b0100))begin
        flag <= 1'b1;
    end  
    else if((dev_id == 2'd0) && (opcode == 4'b0001 || opcode == 4'b0010))begin
        flag <= 1'b0;
    end 
    else begin
        flag <= flag;
    end 
end 
//1s计数器
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_1s <= 28'd0;
    end 
    else if(add_cnt)begin
        if(end_cnt)begin
            cnt_1s <= 28'd0;
        end 
        else begin
            cnt_1s <= cnt_1s + 1;
        end 
    end 
    else begin
        cnt_1s <= cnt_1s;
    end 
end 
assign add_cnt = flag;
assign end_cnt = add_cnt && (cnt_1s == MAX - 1);

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        led <= 4'b0000;
    end 
    else if((dev_id == 2'd0) && (opcode == 4'b0001))begin
        led <= 4'b0000;
    end 
    else if((dev_id == 2'd0) && (opcode == 4'b0010 || opcode == 4'b0100 ))begin
        led <= data;
    end 
    else if(end_cnt)begin
        led <= {led[2: 0], led[3]};
    end 
    else begin
        led <= led;
    end 
end 

endmodule