agi_fpga/hardware/rtl/uart/uart_top.v

module uart_top(
    input   wire         sys_clk    ,
    input   wire         sys_rst_n  ,
    input   wire         rx         ,

    output  wire         tx         ,
    output  wire         led_ready    
);
wire [7: 0] data_byte   ;
wire [7: 0] data_out    ;
wire        ready       ;
wire        comm_finish ;
wire        tx_vld      ;
wire        rx_vld      ;
reg         rcv_start   ;

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        rcv_start <= 1'b1;
    end 
    else if(ready)begin
        rcv_start <= 1'b0;
    end 
    else if(comm_finish)begin
        rcv_start <= 1'b1;
    end 
    else begin
        rcv_start <= rcv_start;
    end 
end 
uart_rx     uart_rx_inst(
.sys_clk        (sys_clk)   ,
.sys_rst_n      (sys_rst_n) ,
.rx_din         (rx)        ,//数据串行输入
.rcv_start      (rcv_start) ,   

.rx_dout        (data_byte) ,//数据并行输出
.rx_vld         (rx_vld)    //输出信号有效
);



uart_tx     uart_tx_inst(
.sys_clk        (sys_clk)   ,
.sys_rst_n      (sys_rst_n) ,
.tx_din         (data_out)  ,//并行输入，接受模块传入
.rx_vld         (rx_vld)    ,//接受模块，串转并有效信
.tx_vld         (tx_vld)    ,  

.tx_dout        (tx)//串行输出
);

device_ready device_ready_inst(
.sys_clk        (sys_clk)   ,
.sys_rst_n      (sys_rst_n) ,
.data_in        (data_byte) ,
.rx_vld         (rx_vld)    ,

.ready          (ready)   
);



command_send command_send_inst(
.sys_clk        (sys_clk)    ,
.sys_rst_n      (sys_rst_n)  ,
.tx_vld         (tx_vld)     ,
    
.comm_finish    (comm_finish),
.data_out       (data_out)
);

led_driver led_driver_inst(
.sys_clk        (sys_clk),
.sys_rst_n      (sys_rst_n),
.rx_data        (data_byte),
    
.led_ready      (led_ready)
);





endmodule