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997 lines
29 KiB
Plaintext
997 lines
29 KiB
Plaintext
5 months ago
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|stark_machine
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sys_clk => sys_clk.IN3
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sys_rst_n => sys_rst_n.IN3
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rx => rx.IN1
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tx <= uart_tx:uart_tx_inst.tx_dout
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led[0] <= circuit_arb:circuit_arb_inst.led
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led[1] <= circuit_arb:circuit_arb_inst.led
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led[2] <= circuit_arb:circuit_arb_inst.led
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led[3] <= circuit_arb:circuit_arb_inst.led
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beep <= circuit_arb:circuit_arb_inst.beep
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seg_led[0] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[1] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[2] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[3] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[4] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[5] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[6] <= circuit_arb:circuit_arb_inst.seg_led
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seg_led[7] <= circuit_arb:circuit_arb_inst.seg_led
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sel_led[0] <= circuit_arb:circuit_arb_inst.sel_led
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sel_led[1] <= circuit_arb:circuit_arb_inst.sel_led
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sel_led[2] <= circuit_arb:circuit_arb_inst.sel_led
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sel_led[3] <= circuit_arb:circuit_arb_inst.sel_led
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sel_led[4] <= circuit_arb:circuit_arb_inst.sel_led
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sel_led[5] <= circuit_arb:circuit_arb_inst.sel_led
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dout <= circuit_arb:circuit_arb_inst.dout
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|stark_machine|uart_rx:uart_rx_inst
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sys_clk => data_reg[0].CLK
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sys_clk => data_reg[1].CLK
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sys_clk => data_reg[2].CLK
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sys_clk => data_reg[3].CLK
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sys_clk => data_reg[4].CLK
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sys_clk => data_reg[5].CLK
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sys_clk => data_reg[6].CLK
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sys_clk => data_reg[7].CLK
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sys_clk => cnt_bit[0].CLK
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sys_clk => cnt_bit[1].CLK
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sys_clk => cnt_bit[2].CLK
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sys_clk => cnt_bit[3].CLK
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sys_clk => cnt_bps[0].CLK
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sys_clk => cnt_bps[1].CLK
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sys_clk => cnt_bps[2].CLK
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sys_clk => cnt_bps[3].CLK
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sys_clk => cnt_bps[4].CLK
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sys_clk => cnt_bps[5].CLK
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sys_clk => cnt_bps[6].CLK
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sys_clk => cnt_bps[7].CLK
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sys_clk => cnt_bps[8].CLK
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sys_clk => cnt_bps[9].CLK
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sys_clk => cnt_bps[10].CLK
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sys_clk => cnt_bps[11].CLK
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sys_clk => cnt_bps[12].CLK
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sys_clk => rx_flag.CLK
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sys_clk => din_reg1.CLK
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sys_clk => din_reg0.CLK
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sys_rst_n => cnt_bps[0].ACLR
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sys_rst_n => cnt_bps[1].ACLR
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sys_rst_n => cnt_bps[2].ACLR
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sys_rst_n => cnt_bps[3].ACLR
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sys_rst_n => cnt_bps[4].ACLR
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sys_rst_n => cnt_bps[5].ACLR
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sys_rst_n => cnt_bps[6].ACLR
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sys_rst_n => cnt_bps[7].ACLR
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sys_rst_n => cnt_bps[8].ACLR
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sys_rst_n => cnt_bps[9].ACLR
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sys_rst_n => cnt_bps[10].ACLR
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sys_rst_n => cnt_bps[11].ACLR
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sys_rst_n => cnt_bps[12].ACLR
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sys_rst_n => din_reg1.PRESET
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sys_rst_n => din_reg0.PRESET
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sys_rst_n => rx_flag.ACLR
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sys_rst_n => cnt_bit[0].ACLR
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sys_rst_n => cnt_bit[1].ACLR
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sys_rst_n => cnt_bit[2].ACLR
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sys_rst_n => cnt_bit[3].ACLR
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rx_din => din_reg0.DATAIN
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rx_dout[0] <= data_reg[0].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[1] <= data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[2] <= data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[3] <= data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[4] <= data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[5] <= data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[6] <= data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
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rx_dout[7] <= data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
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rx_vld <= end_cnt_bit.DB_MAX_OUTPUT_PORT_TYPE
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|stark_machine|uart_tx:uart_tx_inst
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sys_clk => tx_dout~reg0.CLK
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sys_clk => cnt_bit[0].CLK
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sys_clk => cnt_bit[1].CLK
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sys_clk => cnt_bit[2].CLK
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sys_clk => cnt_bit[3].CLK
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sys_clk => cnt_bps[0].CLK
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sys_clk => cnt_bps[1].CLK
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sys_clk => cnt_bps[2].CLK
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sys_clk => cnt_bps[3].CLK
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sys_clk => cnt_bps[4].CLK
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sys_clk => cnt_bps[5].CLK
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sys_clk => cnt_bps[6].CLK
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sys_clk => cnt_bps[7].CLK
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sys_clk => cnt_bps[8].CLK
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sys_clk => cnt_bps[9].CLK
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sys_clk => cnt_bps[10].CLK
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sys_clk => cnt_bps[11].CLK
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sys_clk => cnt_bps[12].CLK
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sys_clk => tx_flag.CLK
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sys_clk => data_reg[0].CLK
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sys_clk => data_reg[1].CLK
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sys_clk => data_reg[2].CLK
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sys_clk => data_reg[3].CLK
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sys_clk => data_reg[4].CLK
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sys_clk => data_reg[5].CLK
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sys_clk => data_reg[6].CLK
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sys_clk => data_reg[7].CLK
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sys_clk => data_reg[8].CLK
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sys_rst_n => cnt_bps[0].ACLR
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sys_rst_n => cnt_bps[1].ACLR
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sys_rst_n => cnt_bps[2].ACLR
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sys_rst_n => cnt_bps[3].ACLR
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sys_rst_n => cnt_bps[4].ACLR
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sys_rst_n => cnt_bps[5].ACLR
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sys_rst_n => cnt_bps[6].ACLR
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sys_rst_n => cnt_bps[7].ACLR
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sys_rst_n => cnt_bps[8].ACLR
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sys_rst_n => cnt_bps[9].ACLR
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sys_rst_n => cnt_bps[10].ACLR
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sys_rst_n => cnt_bps[11].ACLR
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sys_rst_n => cnt_bps[12].ACLR
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sys_rst_n => tx_dout~reg0.PRESET
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sys_rst_n => tx_flag.ACLR
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sys_rst_n => cnt_bit[0].ACLR
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sys_rst_n => cnt_bit[1].ACLR
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sys_rst_n => cnt_bit[2].ACLR
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sys_rst_n => cnt_bit[3].ACLR
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tx_din[0] => data_reg[1].DATAIN
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tx_din[1] => data_reg[2].DATAIN
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tx_din[2] => data_reg[3].DATAIN
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tx_din[3] => data_reg[4].DATAIN
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tx_din[4] => data_reg[5].DATAIN
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tx_din[5] => data_reg[6].DATAIN
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tx_din[6] => data_reg[7].DATAIN
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tx_din[7] => data_reg[8].DATAIN
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rx_vld => tx_flag.OUTPUTSELECT
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rx_vld => data_reg[0].ENA
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rx_vld => data_reg[1].ENA
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rx_vld => data_reg[2].ENA
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rx_vld => data_reg[3].ENA
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rx_vld => data_reg[4].ENA
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rx_vld => data_reg[5].ENA
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rx_vld => data_reg[6].ENA
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rx_vld => data_reg[7].ENA
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rx_vld => data_reg[8].ENA
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tx_vld <= end_cnt_bit.DB_MAX_OUTPUT_PORT_TYPE
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tx_dout <= tx_dout~reg0.DB_MAX_OUTPUT_PORT_TYPE
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|stark_machine|instr_decode:instr_decode_inst
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instruction[0] => data[0].DATAIN
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instruction[1] => data[1].DATAIN
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instruction[2] => data[2].DATAIN
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instruction[3] => data[3].DATAIN
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instruction[4] => data[4].DATAIN
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instruction[5] => data[5].DATAIN
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instruction[6] => data[6].DATAIN
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instruction[7] => data[7].DATAIN
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instruction[8] => opcode[0].DATAIN
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instruction[9] => opcode[1].DATAIN
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instruction[10] => opcode[2].DATAIN
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instruction[11] => opcode[3].DATAIN
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instruction[12] => opcode[4].DATAIN
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instruction[13] => opcode[5].DATAIN
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instruction[14] => opcode[6].DATAIN
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instruction[15] => opcode[7].DATAIN
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instruction[16] => slave_id[0].DATAIN
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instruction[17] => slave_id[1].DATAIN
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instruction[18] => slave_id[2].DATAIN
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instruction[19] => slave_id[3].DATAIN
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instruction[20] => slave_id[4].DATAIN
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instruction[21] => slave_id[5].DATAIN
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instruction[22] => slave_id[6].DATAIN
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instruction[23] => slave_id[7].DATAIN
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opcode[0] <= instruction[8].DB_MAX_OUTPUT_PORT_TYPE
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opcode[1] <= instruction[9].DB_MAX_OUTPUT_PORT_TYPE
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opcode[2] <= instruction[10].DB_MAX_OUTPUT_PORT_TYPE
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opcode[3] <= instruction[11].DB_MAX_OUTPUT_PORT_TYPE
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opcode[4] <= instruction[12].DB_MAX_OUTPUT_PORT_TYPE
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opcode[5] <= instruction[13].DB_MAX_OUTPUT_PORT_TYPE
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opcode[6] <= instruction[14].DB_MAX_OUTPUT_PORT_TYPE
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opcode[7] <= instruction[15].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[0] <= instruction[16].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[1] <= instruction[17].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[2] <= instruction[18].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[3] <= instruction[19].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[4] <= instruction[20].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[5] <= instruction[21].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[6] <= instruction[22].DB_MAX_OUTPUT_PORT_TYPE
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slave_id[7] <= instruction[23].DB_MAX_OUTPUT_PORT_TYPE
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data[0] <= instruction[0].DB_MAX_OUTPUT_PORT_TYPE
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data[1] <= instruction[1].DB_MAX_OUTPUT_PORT_TYPE
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data[2] <= instruction[2].DB_MAX_OUTPUT_PORT_TYPE
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data[3] <= instruction[3].DB_MAX_OUTPUT_PORT_TYPE
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data[4] <= instruction[4].DB_MAX_OUTPUT_PORT_TYPE
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data[5] <= instruction[5].DB_MAX_OUTPUT_PORT_TYPE
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data[6] <= instruction[6].DB_MAX_OUTPUT_PORT_TYPE
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data[7] <= instruction[7].DB_MAX_OUTPUT_PORT_TYPE
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|stark_machine|circuit_arb:circuit_arb_inst
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sys_clk => sys_clk.IN4
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sys_rst_n => sys_rst_n.IN4
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slave_id[0] => Decoder0.IN7
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slave_id[1] => Decoder0.IN6
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slave_id[2] => Decoder0.IN5
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slave_id[3] => Decoder0.IN4
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slave_id[4] => Decoder0.IN3
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slave_id[5] => Decoder0.IN2
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slave_id[6] => Decoder0.IN1
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slave_id[7] => Decoder0.IN0
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opcode[0] => opcode[0].IN4
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opcode[1] => opcode[1].IN4
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opcode[2] => opcode[2].IN4
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opcode[3] => opcode[3].IN4
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opcode[4] => ~NO_FANOUT~
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opcode[5] => ~NO_FANOUT~
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opcode[6] => ~NO_FANOUT~
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opcode[7] => ~NO_FANOUT~
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data[0] => data[0].IN4
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data[1] => data[1].IN4
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data[2] => data[2].IN4
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data[3] => data[3].IN4
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data[4] => ~NO_FANOUT~
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data[5] => ~NO_FANOUT~
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data[6] => ~NO_FANOUT~
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data[7] => ~NO_FANOUT~
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led[0] <= led_circuit:led_circuit_inst.led
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led[1] <= led_circuit:led_circuit_inst.led
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led[2] <= led_circuit:led_circuit_inst.led
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led[3] <= led_circuit:led_circuit_inst.led
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beep <= beep_circuit:beep_circuit_inst.beep
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seg_led[0] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[1] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[2] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[3] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[4] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[5] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[6] <= clock_circuit:clock_circuit_inst.seg_led
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seg_led[7] <= clock_circuit:clock_circuit_inst.seg_led
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sel_led[0] <= clock_circuit:clock_circuit_inst.sel_led
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sel_led[1] <= clock_circuit:clock_circuit_inst.sel_led
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sel_led[2] <= clock_circuit:clock_circuit_inst.sel_led
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sel_led[3] <= clock_circuit:clock_circuit_inst.sel_led
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sel_led[4] <= clock_circuit:clock_circuit_inst.sel_led
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sel_led[5] <= clock_circuit:clock_circuit_inst.sel_led
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dout <= ws2812_circuit:ws2812_circuit_inst.dout
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|stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst
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sys_clk => led[0]~reg0.CLK
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sys_clk => led[1]~reg0.CLK
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sys_clk => led[2]~reg0.CLK
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sys_clk => led[3]~reg0.CLK
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sys_clk => cnt_1s[0].CLK
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sys_clk => cnt_1s[1].CLK
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sys_clk => cnt_1s[2].CLK
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sys_clk => cnt_1s[3].CLK
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sys_clk => cnt_1s[4].CLK
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sys_clk => cnt_1s[5].CLK
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sys_clk => cnt_1s[6].CLK
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sys_clk => cnt_1s[7].CLK
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sys_clk => cnt_1s[8].CLK
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sys_clk => cnt_1s[9].CLK
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sys_clk => cnt_1s[10].CLK
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sys_clk => cnt_1s[11].CLK
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sys_clk => cnt_1s[12].CLK
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sys_clk => cnt_1s[13].CLK
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sys_clk => cnt_1s[14].CLK
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sys_clk => cnt_1s[15].CLK
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sys_clk => cnt_1s[16].CLK
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sys_clk => cnt_1s[17].CLK
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sys_clk => cnt_1s[18].CLK
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sys_clk => cnt_1s[19].CLK
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sys_clk => cnt_1s[20].CLK
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sys_clk => cnt_1s[21].CLK
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sys_clk => cnt_1s[22].CLK
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sys_clk => cnt_1s[23].CLK
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sys_clk => cnt_1s[24].CLK
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sys_clk => cnt_1s[25].CLK
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sys_clk => cnt_1s[26].CLK
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sys_clk => cnt_1s[27].CLK
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sys_clk => flag.CLK
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sys_rst_n => cnt_1s[0].ACLR
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sys_rst_n => cnt_1s[1].ACLR
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sys_rst_n => cnt_1s[2].ACLR
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sys_rst_n => cnt_1s[3].ACLR
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sys_rst_n => cnt_1s[4].ACLR
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sys_rst_n => cnt_1s[5].ACLR
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sys_rst_n => cnt_1s[6].ACLR
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sys_rst_n => cnt_1s[7].ACLR
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sys_rst_n => cnt_1s[8].ACLR
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sys_rst_n => cnt_1s[9].ACLR
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sys_rst_n => cnt_1s[10].ACLR
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sys_rst_n => cnt_1s[11].ACLR
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sys_rst_n => cnt_1s[12].ACLR
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sys_rst_n => cnt_1s[13].ACLR
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sys_rst_n => cnt_1s[14].ACLR
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sys_rst_n => cnt_1s[15].ACLR
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sys_rst_n => cnt_1s[16].ACLR
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sys_rst_n => cnt_1s[17].ACLR
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sys_rst_n => cnt_1s[18].ACLR
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sys_rst_n => cnt_1s[19].ACLR
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sys_rst_n => cnt_1s[20].ACLR
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sys_rst_n => cnt_1s[21].ACLR
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sys_rst_n => cnt_1s[22].ACLR
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sys_rst_n => cnt_1s[23].ACLR
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sys_rst_n => cnt_1s[24].ACLR
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sys_rst_n => cnt_1s[25].ACLR
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sys_rst_n => cnt_1s[26].ACLR
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sys_rst_n => cnt_1s[27].ACLR
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sys_rst_n => led[0]~reg0.ACLR
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sys_rst_n => led[1]~reg0.ACLR
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||
|
sys_rst_n => led[2]~reg0.ACLR
|
||
|
sys_rst_n => led[3]~reg0.ACLR
|
||
|
sys_rst_n => flag.ACLR
|
||
|
opcode[0] => Equal1.IN0
|
||
|
opcode[0] => Equal3.IN3
|
||
|
opcode[0] => Equal4.IN3
|
||
|
opcode[1] => Equal1.IN3
|
||
|
opcode[1] => Equal3.IN0
|
||
|
opcode[1] => Equal4.IN2
|
||
|
opcode[2] => Equal1.IN2
|
||
|
opcode[2] => Equal3.IN2
|
||
|
opcode[2] => Equal4.IN0
|
||
|
opcode[3] => Equal1.IN1
|
||
|
opcode[3] => Equal3.IN1
|
||
|
opcode[3] => Equal4.IN1
|
||
|
data[0] => led.DATAB
|
||
|
data[1] => led.DATAB
|
||
|
data[2] => led.DATAB
|
||
|
data[3] => led.DATAB
|
||
|
dev_id[0] => Equal2.IN1
|
||
|
dev_id[1] => Equal2.IN0
|
||
|
led[0] <= led[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led[1] <= led[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led[2] <= led[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led[3] <= led[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst
|
||
|
sys_clk => sys_clk.IN2
|
||
|
sys_rst_n => sys_rst_n.IN2
|
||
|
dev_id[0] => dev_id[0].IN1
|
||
|
dev_id[1] => dev_id[1].IN1
|
||
|
opcode[0] => opcode[0].IN1
|
||
|
opcode[1] => opcode[1].IN1
|
||
|
opcode[2] => opcode[2].IN1
|
||
|
opcode[3] => opcode[3].IN1
|
||
|
data[0] => data[0].IN1
|
||
|
data[1] => data[1].IN1
|
||
|
data[2] => data[2].IN1
|
||
|
data[3] => data[3].IN1
|
||
|
beep <= pwm_beep:pwm_beep_inst.beep
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst
|
||
|
sys_clk => cnt_freq[0].CLK
|
||
|
sys_clk => cnt_freq[1].CLK
|
||
|
sys_clk => cnt_freq[2].CLK
|
||
|
sys_clk => cnt_freq[3].CLK
|
||
|
sys_clk => cnt_freq[4].CLK
|
||
|
sys_clk => cnt_freq[5].CLK
|
||
|
sys_clk => cnt_freq[6].CLK
|
||
|
sys_clk => cnt_freq[7].CLK
|
||
|
sys_clk => cnt_freq[8].CLK
|
||
|
sys_clk => cnt_freq[9].CLK
|
||
|
sys_clk => cnt_freq[10].CLK
|
||
|
sys_clk => cnt_freq[11].CLK
|
||
|
sys_clk => cnt_freq[12].CLK
|
||
|
sys_clk => cnt_freq[13].CLK
|
||
|
sys_clk => cnt_freq[14].CLK
|
||
|
sys_clk => cnt_freq[15].CLK
|
||
|
sys_clk => cnt_note[0].CLK
|
||
|
sys_clk => cnt_note[1].CLK
|
||
|
sys_clk => cnt_note[2].CLK
|
||
|
sys_clk => cnt_note[3].CLK
|
||
|
sys_clk => cnt_note[4].CLK
|
||
|
sys_clk => cnt_note[5].CLK
|
||
|
sys_clk => cnt_300[0].CLK
|
||
|
sys_clk => cnt_300[1].CLK
|
||
|
sys_clk => cnt_300[2].CLK
|
||
|
sys_clk => cnt_300[3].CLK
|
||
|
sys_clk => cnt_300[4].CLK
|
||
|
sys_clk => cnt_300[5].CLK
|
||
|
sys_clk => cnt_300[6].CLK
|
||
|
sys_clk => cnt_300[7].CLK
|
||
|
sys_clk => cnt_300[8].CLK
|
||
|
sys_clk => cnt_300[9].CLK
|
||
|
sys_clk => cnt_300[10].CLK
|
||
|
sys_clk => cnt_300[11].CLK
|
||
|
sys_clk => cnt_300[12].CLK
|
||
|
sys_clk => cnt_300[13].CLK
|
||
|
sys_clk => cnt_300[14].CLK
|
||
|
sys_clk => cnt_300[15].CLK
|
||
|
sys_clk => cnt_300[16].CLK
|
||
|
sys_clk => cnt_300[17].CLK
|
||
|
sys_clk => cnt_300[18].CLK
|
||
|
sys_clk => cnt_300[19].CLK
|
||
|
sys_clk => cnt_300[20].CLK
|
||
|
sys_clk => cnt_300[21].CLK
|
||
|
sys_clk => cnt_300[22].CLK
|
||
|
sys_clk => cnt_300[23].CLK
|
||
|
sys_clk => start_flag.CLK
|
||
|
sys_rst_n => cnt_300[0].ACLR
|
||
|
sys_rst_n => cnt_300[1].ACLR
|
||
|
sys_rst_n => cnt_300[2].ACLR
|
||
|
sys_rst_n => cnt_300[3].ACLR
|
||
|
sys_rst_n => cnt_300[4].ACLR
|
||
|
sys_rst_n => cnt_300[5].ACLR
|
||
|
sys_rst_n => cnt_300[6].ACLR
|
||
|
sys_rst_n => cnt_300[7].ACLR
|
||
|
sys_rst_n => cnt_300[8].ACLR
|
||
|
sys_rst_n => cnt_300[9].ACLR
|
||
|
sys_rst_n => cnt_300[10].ACLR
|
||
|
sys_rst_n => cnt_300[11].ACLR
|
||
|
sys_rst_n => cnt_300[12].ACLR
|
||
|
sys_rst_n => cnt_300[13].ACLR
|
||
|
sys_rst_n => cnt_300[14].ACLR
|
||
|
sys_rst_n => cnt_300[15].ACLR
|
||
|
sys_rst_n => cnt_300[16].ACLR
|
||
|
sys_rst_n => cnt_300[17].ACLR
|
||
|
sys_rst_n => cnt_300[18].ACLR
|
||
|
sys_rst_n => cnt_300[19].ACLR
|
||
|
sys_rst_n => cnt_300[20].ACLR
|
||
|
sys_rst_n => cnt_300[21].ACLR
|
||
|
sys_rst_n => cnt_300[22].ACLR
|
||
|
sys_rst_n => cnt_300[23].ACLR
|
||
|
sys_rst_n => start_flag.ACLR
|
||
|
sys_rst_n => cnt_note[0].ACLR
|
||
|
sys_rst_n => cnt_note[1].ACLR
|
||
|
sys_rst_n => cnt_note[2].ACLR
|
||
|
sys_rst_n => cnt_note[3].ACLR
|
||
|
sys_rst_n => cnt_note[4].ACLR
|
||
|
sys_rst_n => cnt_note[5].ACLR
|
||
|
sys_rst_n => cnt_freq[0].ACLR
|
||
|
sys_rst_n => cnt_freq[1].ACLR
|
||
|
sys_rst_n => cnt_freq[2].ACLR
|
||
|
sys_rst_n => cnt_freq[3].ACLR
|
||
|
sys_rst_n => cnt_freq[4].ACLR
|
||
|
sys_rst_n => cnt_freq[5].ACLR
|
||
|
sys_rst_n => cnt_freq[6].ACLR
|
||
|
sys_rst_n => cnt_freq[7].ACLR
|
||
|
sys_rst_n => cnt_freq[8].ACLR
|
||
|
sys_rst_n => cnt_freq[9].ACLR
|
||
|
sys_rst_n => cnt_freq[10].ACLR
|
||
|
sys_rst_n => cnt_freq[11].ACLR
|
||
|
sys_rst_n => cnt_freq[12].ACLR
|
||
|
sys_rst_n => cnt_freq[13].ACLR
|
||
|
sys_rst_n => cnt_freq[14].ACLR
|
||
|
sys_rst_n => cnt_freq[15].ACLR
|
||
|
dev_id[0] => Equal1.IN0
|
||
|
dev_id[1] => Equal1.IN1
|
||
|
opcode[0] => Equal0.IN3
|
||
|
opcode[0] => Equal2.IN0
|
||
|
opcode[1] => Equal0.IN0
|
||
|
opcode[1] => Equal2.IN3
|
||
|
opcode[2] => Equal0.IN2
|
||
|
opcode[2] => Equal2.IN2
|
||
|
opcode[3] => Equal0.IN1
|
||
|
opcode[3] => Equal2.IN1
|
||
|
data[0] => Equal6.IN7
|
||
|
data[0] => Equal7.IN7
|
||
|
data[1] => Equal6.IN6
|
||
|
data[1] => Equal7.IN6
|
||
|
data[2] => Equal6.IN5
|
||
|
data[2] => Equal7.IN5
|
||
|
data[3] => Equal6.IN4
|
||
|
data[3] => Equal7.IN4
|
||
|
pwm <= LessThan0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|pwm_beep:pwm_beep_inst
|
||
|
sys_clk => beep~reg0.CLK
|
||
|
sys_rst_n => beep~reg0.PRESET
|
||
|
pwm => beep~reg0.DATAIN
|
||
|
beep <= beep~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst
|
||
|
sys_clk => sys_clk.IN2
|
||
|
sys_rst_n => sys_rst_n.IN2
|
||
|
opcode[0] => opcode[0].IN2
|
||
|
opcode[1] => opcode[1].IN2
|
||
|
opcode[2] => opcode[2].IN2
|
||
|
opcode[3] => opcode[3].IN2
|
||
|
data[0] => ~NO_FANOUT~
|
||
|
data[1] => ~NO_FANOUT~
|
||
|
data[2] => ~NO_FANOUT~
|
||
|
data[3] => ~NO_FANOUT~
|
||
|
dev_id[0] => dev_id[0].IN2
|
||
|
dev_id[1] => dev_id[1].IN2
|
||
|
seg_led[0] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[1] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[2] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[3] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[4] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[5] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[6] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
seg_led[7] <= timer_decoder:timer_decoder_inst.seg_led
|
||
|
sel_led[0] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
sel_led[1] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
sel_led[2] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
sel_led[3] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
sel_led[4] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
sel_led[5] <= timer_decoder:timer_decoder_inst.sel_led
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst
|
||
|
sys_clk => cnt_day[0].CLK
|
||
|
sys_clk => cnt_day[1].CLK
|
||
|
sys_clk => cnt_day[2].CLK
|
||
|
sys_clk => cnt_day[3].CLK
|
||
|
sys_clk => cnt_day[4].CLK
|
||
|
sys_clk => cnt_day[5].CLK
|
||
|
sys_clk => cnt_day[6].CLK
|
||
|
sys_clk => cnt_day[7].CLK
|
||
|
sys_clk => cnt_day[8].CLK
|
||
|
sys_clk => cnt_day[9].CLK
|
||
|
sys_clk => cnt_day[10].CLK
|
||
|
sys_clk => cnt_day[11].CLK
|
||
|
sys_clk => cnt_day[12].CLK
|
||
|
sys_clk => cnt_day[13].CLK
|
||
|
sys_clk => cnt_day[14].CLK
|
||
|
sys_clk => cnt_day[15].CLK
|
||
|
sys_clk => cnt_day[16].CLK
|
||
|
sys_clk => cnt_s[0].CLK
|
||
|
sys_clk => cnt_s[1].CLK
|
||
|
sys_clk => cnt_s[2].CLK
|
||
|
sys_clk => cnt_s[3].CLK
|
||
|
sys_clk => cnt_s[4].CLK
|
||
|
sys_clk => cnt_s[5].CLK
|
||
|
sys_clk => cnt_s[6].CLK
|
||
|
sys_clk => cnt_s[7].CLK
|
||
|
sys_clk => cnt_s[8].CLK
|
||
|
sys_clk => cnt_s[9].CLK
|
||
|
sys_clk => cnt_s[10].CLK
|
||
|
sys_clk => cnt_s[11].CLK
|
||
|
sys_clk => cnt_s[12].CLK
|
||
|
sys_clk => cnt_s[13].CLK
|
||
|
sys_clk => cnt_s[14].CLK
|
||
|
sys_clk => cnt_s[15].CLK
|
||
|
sys_clk => cnt_s[16].CLK
|
||
|
sys_clk => cnt_s[17].CLK
|
||
|
sys_clk => cnt_s[18].CLK
|
||
|
sys_clk => cnt_s[19].CLK
|
||
|
sys_clk => cnt_s[20].CLK
|
||
|
sys_clk => cnt_s[21].CLK
|
||
|
sys_clk => cnt_s[22].CLK
|
||
|
sys_clk => cnt_s[23].CLK
|
||
|
sys_clk => cnt_s[24].CLK
|
||
|
sys_clk => cnt_s[25].CLK
|
||
|
sys_clk => cnt_s[26].CLK
|
||
|
sys_clk => cnt_s[27].CLK
|
||
|
sys_clk => start_flag.CLK
|
||
|
sys_rst_n => cnt_s[0].ACLR
|
||
|
sys_rst_n => cnt_s[1].ACLR
|
||
|
sys_rst_n => cnt_s[2].ACLR
|
||
|
sys_rst_n => cnt_s[3].ACLR
|
||
|
sys_rst_n => cnt_s[4].ACLR
|
||
|
sys_rst_n => cnt_s[5].ACLR
|
||
|
sys_rst_n => cnt_s[6].ACLR
|
||
|
sys_rst_n => cnt_s[7].ACLR
|
||
|
sys_rst_n => cnt_s[8].ACLR
|
||
|
sys_rst_n => cnt_s[9].ACLR
|
||
|
sys_rst_n => cnt_s[10].ACLR
|
||
|
sys_rst_n => cnt_s[11].ACLR
|
||
|
sys_rst_n => cnt_s[12].ACLR
|
||
|
sys_rst_n => cnt_s[13].ACLR
|
||
|
sys_rst_n => cnt_s[14].ACLR
|
||
|
sys_rst_n => cnt_s[15].ACLR
|
||
|
sys_rst_n => cnt_s[16].ACLR
|
||
|
sys_rst_n => cnt_s[17].ACLR
|
||
|
sys_rst_n => cnt_s[18].ACLR
|
||
|
sys_rst_n => cnt_s[19].ACLR
|
||
|
sys_rst_n => cnt_s[20].ACLR
|
||
|
sys_rst_n => cnt_s[21].ACLR
|
||
|
sys_rst_n => cnt_s[22].ACLR
|
||
|
sys_rst_n => cnt_s[23].ACLR
|
||
|
sys_rst_n => cnt_s[24].ACLR
|
||
|
sys_rst_n => cnt_s[25].ACLR
|
||
|
sys_rst_n => cnt_s[26].ACLR
|
||
|
sys_rst_n => cnt_s[27].ACLR
|
||
|
sys_rst_n => start_flag.ACLR
|
||
|
sys_rst_n => cnt_day[0].ACLR
|
||
|
sys_rst_n => cnt_day[1].ACLR
|
||
|
sys_rst_n => cnt_day[2].ACLR
|
||
|
sys_rst_n => cnt_day[3].ACLR
|
||
|
sys_rst_n => cnt_day[4].ACLR
|
||
|
sys_rst_n => cnt_day[5].ACLR
|
||
|
sys_rst_n => cnt_day[6].ACLR
|
||
|
sys_rst_n => cnt_day[7].ACLR
|
||
|
sys_rst_n => cnt_day[8].ACLR
|
||
|
sys_rst_n => cnt_day[9].ACLR
|
||
|
sys_rst_n => cnt_day[10].ACLR
|
||
|
sys_rst_n => cnt_day[11].ACLR
|
||
|
sys_rst_n => cnt_day[12].ACLR
|
||
|
sys_rst_n => cnt_day[13].ACLR
|
||
|
sys_rst_n => cnt_day[14].ACLR
|
||
|
sys_rst_n => cnt_day[15].ACLR
|
||
|
sys_rst_n => cnt_day[16].ACLR
|
||
|
dev_id[0] => Equal1.IN1
|
||
|
dev_id[1] => Equal1.IN0
|
||
|
opcode[0] => Equal0.IN0
|
||
|
opcode[0] => Equal2.IN3
|
||
|
opcode[1] => Equal0.IN3
|
||
|
opcode[1] => Equal2.IN0
|
||
|
opcode[2] => Equal0.IN2
|
||
|
opcode[2] => Equal2.IN2
|
||
|
opcode[3] => Equal0.IN1
|
||
|
opcode[3] => Equal2.IN1
|
||
|
hour[0] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
hour[1] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
hour[2] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
hour[3] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
hour[4] <= Div0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[0] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[1] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[2] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[3] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[4] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
min[5] <= Div1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[0] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[1] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[2] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[3] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[4] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sec[5] <= Mod1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst
|
||
|
sys_clk => sel_led[0]~reg0.CLK
|
||
|
sys_clk => sel_led[1]~reg0.CLK
|
||
|
sys_clk => sel_led[2]~reg0.CLK
|
||
|
sys_clk => sel_led[3]~reg0.CLK
|
||
|
sys_clk => sel_led[4]~reg0.CLK
|
||
|
sys_clk => sel_led[5]~reg0.CLK
|
||
|
sys_clk => cnt_fps[0].CLK
|
||
|
sys_clk => cnt_fps[1].CLK
|
||
|
sys_clk => cnt_fps[2].CLK
|
||
|
sys_clk => cnt_fps[3].CLK
|
||
|
sys_clk => cnt_fps[4].CLK
|
||
|
sys_clk => cnt_fps[5].CLK
|
||
|
sys_clk => cnt_fps[6].CLK
|
||
|
sys_clk => cnt_fps[7].CLK
|
||
|
sys_clk => cnt_fps[8].CLK
|
||
|
sys_clk => cnt_fps[9].CLK
|
||
|
sys_clk => start_flag.CLK
|
||
|
sys_rst_n => cnt_fps[0].ACLR
|
||
|
sys_rst_n => cnt_fps[1].ACLR
|
||
|
sys_rst_n => cnt_fps[2].ACLR
|
||
|
sys_rst_n => cnt_fps[3].ACLR
|
||
|
sys_rst_n => cnt_fps[4].ACLR
|
||
|
sys_rst_n => cnt_fps[5].ACLR
|
||
|
sys_rst_n => cnt_fps[6].ACLR
|
||
|
sys_rst_n => cnt_fps[7].ACLR
|
||
|
sys_rst_n => cnt_fps[8].ACLR
|
||
|
sys_rst_n => cnt_fps[9].ACLR
|
||
|
sys_rst_n => sel_led[0]~reg0.PRESET
|
||
|
sys_rst_n => sel_led[1]~reg0.PRESET
|
||
|
sys_rst_n => sel_led[2]~reg0.PRESET
|
||
|
sys_rst_n => sel_led[3]~reg0.PRESET
|
||
|
sys_rst_n => sel_led[4]~reg0.PRESET
|
||
|
sys_rst_n => sel_led[5]~reg0.PRESET
|
||
|
sys_rst_n => start_flag.ACLR
|
||
|
dev_id[0] => Equal1.IN0
|
||
|
dev_id[1] => Equal1.IN1
|
||
|
opcode[0] => Equal0.IN3
|
||
|
opcode[0] => Equal2.IN2
|
||
|
opcode[1] => Equal0.IN2
|
||
|
opcode[1] => Equal2.IN3
|
||
|
opcode[2] => Equal0.IN1
|
||
|
opcode[2] => Equal2.IN1
|
||
|
opcode[3] => Equal0.IN0
|
||
|
opcode[3] => Equal2.IN0
|
||
|
hour[0] => Div0.IN8
|
||
|
hour[0] => Mod0.IN8
|
||
|
hour[1] => Div0.IN7
|
||
|
hour[1] => Mod0.IN7
|
||
|
hour[2] => Div0.IN6
|
||
|
hour[2] => Mod0.IN6
|
||
|
hour[3] => Div0.IN5
|
||
|
hour[3] => Mod0.IN5
|
||
|
hour[4] => Div0.IN4
|
||
|
hour[4] => Mod0.IN4
|
||
|
min[0] => Div1.IN9
|
||
|
min[0] => Mod1.IN9
|
||
|
min[1] => Div1.IN8
|
||
|
min[1] => Mod1.IN8
|
||
|
min[2] => Div1.IN7
|
||
|
min[2] => Mod1.IN7
|
||
|
min[3] => Div1.IN6
|
||
|
min[3] => Mod1.IN6
|
||
|
min[4] => Div1.IN5
|
||
|
min[4] => Mod1.IN5
|
||
|
min[5] => Div1.IN4
|
||
|
min[5] => Mod1.IN4
|
||
|
sec[0] => Div2.IN9
|
||
|
sec[0] => Mod2.IN9
|
||
|
sec[1] => Div2.IN8
|
||
|
sec[1] => Mod2.IN8
|
||
|
sec[2] => Div2.IN7
|
||
|
sec[2] => Mod2.IN7
|
||
|
sec[3] => Div2.IN6
|
||
|
sec[3] => Mod2.IN6
|
||
|
sec[4] => Div2.IN5
|
||
|
sec[4] => Mod2.IN5
|
||
|
sec[5] => Div2.IN4
|
||
|
sec[5] => Mod2.IN4
|
||
|
seg_led[0] <= seg_led.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[1] <= seg_led.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[2] <= Decoder1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[3] <= WideOr4.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[4] <= WideOr3.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[5] <= WideOr2.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[6] <= WideOr1.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
seg_led[7] <= <VCC>
|
||
|
sel_led[0] <= sel_led[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sel_led[1] <= sel_led[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sel_led[2] <= sel_led[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sel_led[3] <= sel_led[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sel_led[4] <= sel_led[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
sel_led[5] <= sel_led[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst
|
||
|
sys_clk => sys_clk.IN1
|
||
|
sys_rst_n => sys_rst_n.IN1
|
||
|
opcode[0] => opcode[0].IN1
|
||
|
opcode[1] => opcode[1].IN1
|
||
|
opcode[2] => opcode[2].IN1
|
||
|
opcode[3] => opcode[3].IN1
|
||
|
data[0] => data[0].IN1
|
||
|
data[1] => data[1].IN1
|
||
|
data[2] => data[2].IN1
|
||
|
data[3] => data[3].IN1
|
||
|
dev_id[0] => dev_id[0].IN1
|
||
|
dev_id[1] => dev_id[1].IN1
|
||
|
dout <= ws2812_ctrl:ws2812_ctrl_inst.dout
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst
|
||
|
sys_clk => frame[0]~reg0.CLK
|
||
|
sys_clk => frame[1]~reg0.CLK
|
||
|
sys_clk => cnt_rst[0].CLK
|
||
|
sys_clk => cnt_rst[1].CLK
|
||
|
sys_clk => cnt_rst[2].CLK
|
||
|
sys_clk => cnt_rst[3].CLK
|
||
|
sys_clk => cnt_rst[4].CLK
|
||
|
sys_clk => cnt_rst[5].CLK
|
||
|
sys_clk => cnt_rst[6].CLK
|
||
|
sys_clk => cnt_rst[7].CLK
|
||
|
sys_clk => cnt_rst[8].CLK
|
||
|
sys_clk => cnt_rst[9].CLK
|
||
|
sys_clk => cnt_rst[10].CLK
|
||
|
sys_clk => cnt_rst[11].CLK
|
||
|
sys_clk => cnt_rst[12].CLK
|
||
|
sys_clk => cnt_rst[13].CLK
|
||
|
sys_clk => cnt_rst[14].CLK
|
||
|
sys_clk => cnt_rst[15].CLK
|
||
|
sys_clk => cnt_rst[16].CLK
|
||
|
sys_clk => cnt_rst[17].CLK
|
||
|
sys_clk => cnt_rst[18].CLK
|
||
|
sys_clk => cnt_rst[19].CLK
|
||
|
sys_clk => cnt_rst[20].CLK
|
||
|
sys_clk => cnt_rst[21].CLK
|
||
|
sys_clk => cnt_rst[22].CLK
|
||
|
sys_clk => cnt_rst[23].CLK
|
||
|
sys_clk => cnt_rst[24].CLK
|
||
|
sys_clk => cnt_rst[25].CLK
|
||
|
sys_clk => rst_flag.CLK
|
||
|
sys_clk => led_num[0]~reg0.CLK
|
||
|
sys_clk => led_num[1]~reg0.CLK
|
||
|
sys_clk => led_num[2]~reg0.CLK
|
||
|
sys_clk => led_num[3]~reg0.CLK
|
||
|
sys_clk => led_num[4]~reg0.CLK
|
||
|
sys_clk => led_num[5]~reg0.CLK
|
||
|
sys_clk => led_num[6]~reg0.CLK
|
||
|
sys_clk => bit_num[0]~reg0.CLK
|
||
|
sys_clk => bit_num[1]~reg0.CLK
|
||
|
sys_clk => bit_num[2]~reg0.CLK
|
||
|
sys_clk => bit_num[3]~reg0.CLK
|
||
|
sys_clk => bit_num[4]~reg0.CLK
|
||
|
sys_clk => cnt_1[0].CLK
|
||
|
sys_clk => cnt_1[1].CLK
|
||
|
sys_clk => cnt_1[2].CLK
|
||
|
sys_clk => cnt_1[3].CLK
|
||
|
sys_clk => cnt_1[4].CLK
|
||
|
sys_clk => cnt_1[5].CLK
|
||
|
sys_clk => cnt_0[0].CLK
|
||
|
sys_clk => cnt_0[1].CLK
|
||
|
sys_clk => cnt_0[2].CLK
|
||
|
sys_clk => cnt_0[3].CLK
|
||
|
sys_clk => cnt_0[4].CLK
|
||
|
sys_clk => cnt_0[5].CLK
|
||
|
sys_clk => start_flag.CLK
|
||
|
sys_rst_n => led_num[0]~reg0.ACLR
|
||
|
sys_rst_n => led_num[1]~reg0.ACLR
|
||
|
sys_rst_n => led_num[2]~reg0.ACLR
|
||
|
sys_rst_n => led_num[3]~reg0.ACLR
|
||
|
sys_rst_n => led_num[4]~reg0.ACLR
|
||
|
sys_rst_n => led_num[5]~reg0.ACLR
|
||
|
sys_rst_n => led_num[6]~reg0.ACLR
|
||
|
sys_rst_n => bit_num[0]~reg0.ACLR
|
||
|
sys_rst_n => bit_num[1]~reg0.ACLR
|
||
|
sys_rst_n => bit_num[2]~reg0.ACLR
|
||
|
sys_rst_n => bit_num[3]~reg0.ACLR
|
||
|
sys_rst_n => bit_num[4]~reg0.ACLR
|
||
|
sys_rst_n => frame[0]~reg0.ACLR
|
||
|
sys_rst_n => frame[1]~reg0.ACLR
|
||
|
sys_rst_n => start_flag.ACLR
|
||
|
sys_rst_n => cnt_0[0].ACLR
|
||
|
sys_rst_n => cnt_0[1].ACLR
|
||
|
sys_rst_n => cnt_0[2].ACLR
|
||
|
sys_rst_n => cnt_0[3].ACLR
|
||
|
sys_rst_n => cnt_0[4].ACLR
|
||
|
sys_rst_n => cnt_0[5].ACLR
|
||
|
sys_rst_n => cnt_1[0].ACLR
|
||
|
sys_rst_n => cnt_1[1].ACLR
|
||
|
sys_rst_n => cnt_1[2].ACLR
|
||
|
sys_rst_n => cnt_1[3].ACLR
|
||
|
sys_rst_n => cnt_1[4].ACLR
|
||
|
sys_rst_n => cnt_1[5].ACLR
|
||
|
sys_rst_n => rst_flag.ACLR
|
||
|
sys_rst_n => cnt_rst[0].ACLR
|
||
|
sys_rst_n => cnt_rst[1].ACLR
|
||
|
sys_rst_n => cnt_rst[2].ACLR
|
||
|
sys_rst_n => cnt_rst[3].ACLR
|
||
|
sys_rst_n => cnt_rst[4].ACLR
|
||
|
sys_rst_n => cnt_rst[5].ACLR
|
||
|
sys_rst_n => cnt_rst[6].ACLR
|
||
|
sys_rst_n => cnt_rst[7].ACLR
|
||
|
sys_rst_n => cnt_rst[8].ACLR
|
||
|
sys_rst_n => cnt_rst[9].ACLR
|
||
|
sys_rst_n => cnt_rst[10].ACLR
|
||
|
sys_rst_n => cnt_rst[11].ACLR
|
||
|
sys_rst_n => cnt_rst[12].ACLR
|
||
|
sys_rst_n => cnt_rst[13].ACLR
|
||
|
sys_rst_n => cnt_rst[14].ACLR
|
||
|
sys_rst_n => cnt_rst[15].ACLR
|
||
|
sys_rst_n => cnt_rst[16].ACLR
|
||
|
sys_rst_n => cnt_rst[17].ACLR
|
||
|
sys_rst_n => cnt_rst[18].ACLR
|
||
|
sys_rst_n => cnt_rst[19].ACLR
|
||
|
sys_rst_n => cnt_rst[20].ACLR
|
||
|
sys_rst_n => cnt_rst[21].ACLR
|
||
|
sys_rst_n => cnt_rst[22].ACLR
|
||
|
sys_rst_n => cnt_rst[23].ACLR
|
||
|
sys_rst_n => cnt_rst[24].ACLR
|
||
|
sys_rst_n => cnt_rst[25].ACLR
|
||
|
bit => add_cnt_1.IN1
|
||
|
bit => dout.IN1
|
||
|
bit => add_cnt_0.IN1
|
||
|
bit => dout.IN1
|
||
|
opcode[0] => Equal0.IN3
|
||
|
opcode[0] => Equal4.IN0
|
||
|
opcode[1] => Equal0.IN0
|
||
|
opcode[1] => Equal4.IN3
|
||
|
opcode[2] => Equal0.IN2
|
||
|
opcode[2] => Equal4.IN2
|
||
|
opcode[3] => Equal0.IN1
|
||
|
opcode[3] => Equal4.IN1
|
||
|
data[0] => ~NO_FANOUT~
|
||
|
data[1] => ~NO_FANOUT~
|
||
|
data[2] => ~NO_FANOUT~
|
||
|
data[3] => ~NO_FANOUT~
|
||
|
dev_id[0] => Equal3.IN1
|
||
|
dev_id[1] => Equal3.IN0
|
||
|
bit_num[0] <= bit_num[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
bit_num[1] <= bit_num[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
bit_num[2] <= bit_num[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
bit_num[3] <= bit_num[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
bit_num[4] <= bit_num[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[0] <= led_num[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[1] <= led_num[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[2] <= led_num[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[3] <= led_num[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[4] <= led_num[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[5] <= led_num[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
led_num[6] <= led_num[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
frame[0] <= frame[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
frame[1] <= frame[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
dout <= dout.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|
||
|
|stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|data_cfg:data_cfg_inst
|
||
|
bit_num[0] => Mux15.IN19
|
||
|
bit_num[1] => Mux15.IN18
|
||
|
bit_num[2] => Mux15.IN17
|
||
|
bit_num[3] => Add1.IN2
|
||
|
bit_num[4] => Add1.IN1
|
||
|
led_num[0] => Mux0.IN263
|
||
|
led_num[0] => Mux1.IN263
|
||
|
led_num[0] => Mux2.IN263
|
||
|
led_num[0] => Mux3.IN263
|
||
|
led_num[0] => Mux4.IN263
|
||
|
led_num[0] => Mux5.IN263
|
||
|
led_num[0] => Mux6.IN263
|
||
|
led_num[0] => Mux7.IN263
|
||
|
led_num[0] => Mux8.IN263
|
||
|
led_num[0] => Mux9.IN263
|
||
|
led_num[0] => Mux10.IN263
|
||
|
led_num[0] => Mux11.IN263
|
||
|
led_num[0] => Mux12.IN263
|
||
|
led_num[0] => Mux13.IN263
|
||
|
led_num[0] => Mux14.IN263
|
||
|
led_num[1] => Mux0.IN262
|
||
|
led_num[1] => Mux1.IN262
|
||
|
led_num[1] => Mux2.IN262
|
||
|
led_num[1] => Mux3.IN262
|
||
|
led_num[1] => Mux4.IN262
|
||
|
led_num[1] => Mux5.IN262
|
||
|
led_num[1] => Mux6.IN262
|
||
|
led_num[1] => Mux7.IN262
|
||
|
led_num[1] => Mux8.IN262
|
||
|
led_num[1] => Mux9.IN262
|
||
|
led_num[1] => Mux10.IN262
|
||
|
led_num[1] => Mux11.IN262
|
||
|
led_num[1] => Mux12.IN262
|
||
|
led_num[1] => Mux13.IN262
|
||
|
led_num[1] => Mux14.IN262
|
||
|
led_num[2] => Mux0.IN261
|
||
|
led_num[2] => Mux1.IN261
|
||
|
led_num[2] => Mux2.IN261
|
||
|
led_num[2] => Mux3.IN261
|
||
|
led_num[2] => Mux4.IN261
|
||
|
led_num[2] => Mux5.IN261
|
||
|
led_num[2] => Mux6.IN261
|
||
|
led_num[2] => Mux7.IN261
|
||
|
led_num[2] => Mux8.IN261
|
||
|
led_num[2] => Mux9.IN261
|
||
|
led_num[2] => Mux10.IN261
|
||
|
led_num[2] => Mux11.IN261
|
||
|
led_num[2] => Mux12.IN261
|
||
|
led_num[2] => Mux13.IN261
|
||
|
led_num[2] => Mux14.IN261
|
||
|
led_num[3] => Mux0.IN260
|
||
|
led_num[3] => Mux1.IN260
|
||
|
led_num[3] => Mux2.IN260
|
||
|
led_num[3] => Mux3.IN260
|
||
|
led_num[3] => Mux4.IN260
|
||
|
led_num[3] => Mux5.IN260
|
||
|
led_num[3] => Mux6.IN260
|
||
|
led_num[3] => Mux7.IN260
|
||
|
led_num[3] => Mux8.IN260
|
||
|
led_num[3] => Mux9.IN260
|
||
|
led_num[3] => Mux10.IN260
|
||
|
led_num[3] => Mux11.IN260
|
||
|
led_num[3] => Mux12.IN260
|
||
|
led_num[3] => Mux13.IN260
|
||
|
led_num[3] => Mux14.IN260
|
||
|
led_num[4] => Mux0.IN259
|
||
|
led_num[4] => Mux1.IN259
|
||
|
led_num[4] => Mux2.IN259
|
||
|
led_num[4] => Mux3.IN259
|
||
|
led_num[4] => Mux4.IN259
|
||
|
led_num[4] => Mux5.IN259
|
||
|
led_num[4] => Mux6.IN259
|
||
|
led_num[4] => Mux7.IN259
|
||
|
led_num[4] => Mux8.IN259
|
||
|
led_num[4] => Mux9.IN259
|
||
|
led_num[4] => Mux10.IN259
|
||
|
led_num[4] => Mux11.IN259
|
||
|
led_num[4] => Mux12.IN259
|
||
|
led_num[4] => Mux13.IN259
|
||
|
led_num[4] => Mux14.IN259
|
||
|
led_num[5] => Mux0.IN258
|
||
|
led_num[5] => Mux1.IN258
|
||
|
led_num[5] => Mux2.IN258
|
||
|
led_num[5] => Mux3.IN258
|
||
|
led_num[5] => Mux4.IN258
|
||
|
led_num[5] => Mux5.IN258
|
||
|
led_num[5] => Mux6.IN258
|
||
|
led_num[5] => Mux7.IN258
|
||
|
led_num[5] => Mux8.IN258
|
||
|
led_num[5] => Mux9.IN258
|
||
|
led_num[5] => Mux10.IN258
|
||
|
led_num[5] => Mux11.IN258
|
||
|
led_num[5] => Mux12.IN258
|
||
|
led_num[5] => Mux13.IN258
|
||
|
led_num[5] => Mux14.IN258
|
||
|
led_num[6] => Add0.IN2
|
||
|
frame[0] => Add0.IN4
|
||
|
frame[1] => Add0.IN3
|
||
|
bit <= Mux15.DB_MAX_OUTPUT_PORT_TYPE
|
||
|
|
||
|
|