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146 lines
94 KiB
Plaintext
146 lines
94 KiB
Plaintext
5 months ago
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{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1718872033766 ""}
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{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718872033766 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 20 16:27:13 2024 " "Processing started: Thu Jun 20 16:27:13 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718872033766 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872033766 ""}
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{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga " "Command: quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872033766 ""}
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{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1718872034391 ""}
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{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1718872034391 ""}
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{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "uart_tx.v(28) " "Verilog HDL warning at uart_tx.v(28): extended using \"x\" or \"z\"" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 28 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1718872052785 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052792 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052792 ""}
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{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "uart_rx.v(96) " "Verilog HDL warning at uart_rx.v(96): extended using \"x\" or \"z\"" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 96 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1718872052807 ""}
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{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "uart_rx.v(94) " "Verilog HDL information at uart_rx.v(94): always construct contains both blocking and non-blocking assignments" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 94 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1718872052808 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052809 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/param.v 0 0 " "Found 0 design units, including 0 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/param.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052814 ""}
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{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit ws2812_ctrl.v(4) " "Verilog HDL Declaration warning at ws2812_ctrl.v(4): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 4 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718872052833 ""}
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{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "bit BIT ws2812_ctrl.v(4) " "Verilog HDL Declaration information at ws2812_ctrl.v(4): object \"bit\" differs only in case from object \"BIT\" in the same scope" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 4 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1718872052834 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ws2812_ctrl " "Found entity 1: ws2812_ctrl" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052835 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052835 ""}
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{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit ws2812_circuit.v(14) " "Verilog HDL Declaration warning at ws2812_circuit.v(14): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/ws2812_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 14 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718872052846 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ws2812_circuit " "Found entity 1: ws2812_circuit" { } { { "../rtl/ws2812/ws2812_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052847 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052847 ""}
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{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit data_cfg.v(7) " "Verilog HDL Declaration warning at data_cfg.v(7): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/data_cfg.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" 7 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718872052862 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_cfg " "Found entity 1: data_cfg" { } { { "../rtl/ws2812/data_cfg.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052865 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052865 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_decoder " "Found entity 1: timer_decoder" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052879 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052879 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer " "Found entity 1: timer" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052893 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052893 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_circuit " "Found entity 1: clock_circuit" { } { { "../rtl/digit_led/clock_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052905 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052905 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_beep " "Found entity 1: pwm_beep" { } { { "../rtl/beep/pwm_beep.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052915 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052915 ""}
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{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "6 freq_select.v(12) " "Verilog HDL Expression warning at freq_select.v(12): truncated literal to match 6 bits" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 12 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1718872052930 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/freq_select.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/freq_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 freq_select " "Found entity 1: freq_select" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052932 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052932 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 beep_circuit " "Found entity 1: beep_circuit" { } { { "../rtl/beep/beep_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052942 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052942 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/led/led_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/led/led_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 led_circuit " "Found entity 1: led_circuit" { } { { "../rtl/led/led_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052955 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052955 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_tx.v " "Can't analyze file -- file ../rtl/uart_tx.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718872052959 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_top.v " "Can't analyze file -- file ../rtl/uart_top.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718872052961 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_rx.v " "Can't analyze file -- file ../rtl/uart_rx.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718872052962 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/stark_machine.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/stark_machine.v" { { "Info" "ISGN_ENTITY_NAME" "1 stark_machine " "Found entity 1: stark_machine" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052968 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052968 ""}
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{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/param.v " "Can't analyze file -- file ../rtl/param.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718872052970 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/key_filter.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/key_filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_filter " "Found entity 1: key_filter" { } { { "../rtl/key_filter.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/key_filter.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052985 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052985 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/instr_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/instr_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 instr_decode " "Found entity 1: instr_decode" { } { { "../rtl/instr_decode.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/instr_decode.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872052996 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872052996 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/circuit_arb.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/circuit_arb.v" { { "Info" "ISGN_ENTITY_NAME" "1 circuit_arb " "Found entity 1: circuit_arb" { } { { "../rtl/circuit_arb.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872053007 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053007 ""}
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{ "Info" "ISGN_START_ELABORATION_TOP" "stark_machine " "Elaborating entity \"stark_machine\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1718872053119 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:uart_rx_inst " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:uart_rx_inst\"" { } { { "../rtl/stark_machine.v" "uart_rx_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053163 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:uart_tx_inst " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:uart_tx_inst\"" { } { { "../rtl/stark_machine.v" "uart_tx_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053189 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instr_decode instr_decode:instr_decode_inst " "Elaborating entity \"instr_decode\" for hierarchy \"instr_decode:instr_decode_inst\"" { } { { "../rtl/stark_machine.v" "instr_decode_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053213 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuit_arb circuit_arb:circuit_arb_inst " "Elaborating entity \"circuit_arb\" for hierarchy \"circuit_arb:circuit_arb_inst\"" { } { { "../rtl/stark_machine.v" "circuit_arb_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 87 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053228 ""}
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{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_circuit circuit_arb:circuit_arb_inst\|led_circuit:led_circuit_inst " "Elaborating entity \"led_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|led_circuit:led_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "led_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053243 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 led_circuit.v(39) " "Verilog HDL assignment warning at led_circuit.v(39): truncated value with size 32 to match size of target (28)" { } { { "../rtl/led/led_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v" 39 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053244 "|stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "beep_circuit circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst " "Elaborating entity \"beep_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "beep_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053262 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_select circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst " "Elaborating entity \"freq_select\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\"" { } { { "../rtl/beep/beep_circuit.v" "freq_select_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053262 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "freq_select.v(116) " "Verilog HDL Case Statement warning at freq_select.v(116): incomplete case statement has no default case item" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1718872053277 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "freq_select.v(116) " "Verilog HDL Case Statement information at freq_select.v(116): all case item expressions in this case statement are onehot" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1718872053277 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "note freq_select.v(116) " "Verilog HDL Always Construct warning at freq_select.v(116): inferring latch(es) for variable \"note\", which holds its previous value in one or more paths through the always construct" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1718872053277 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[0\] freq_select.v(116) " "Inferred latch for \"note\[0\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[1\] freq_select.v(116) " "Inferred latch for \"note\[1\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[2\] freq_select.v(116) " "Inferred latch for \"note\[2\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[3\] freq_select.v(116) " "Inferred latch for \"note\[3\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[4\] freq_select.v(116) " "Inferred latch for \"note\[4\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[5\] freq_select.v(116) " "Inferred latch for \"note\[5\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872053279 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_beep circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|pwm_beep:pwm_beep_inst " "Elaborating entity \"pwm_beep\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|pwm_beep:pwm_beep_inst\"" { } { { "../rtl/beep/beep_circuit.v" "pwm_beep_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053298 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_circuit circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst " "Elaborating entity \"clock_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "clock_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053308 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst " "Elaborating entity \"timer\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\"" { } { { "../rtl/digit_led/clock_circuit.v" "timer_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053315 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 timer.v(79) " "Verilog HDL assignment warning at timer.v(79): truncated value with size 32 to match size of target (5)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053317 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 timer.v(80) " "Verilog HDL assignment warning at timer.v(80): truncated value with size 32 to match size of target (6)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053317 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 timer.v(81) " "Verilog HDL assignment warning at timer.v(81): truncated value with size 32 to match size of target (6)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053317 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_decoder circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst " "Elaborating entity \"timer_decoder\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\"" { } { { "../rtl/digit_led/clock_circuit.v" "timer_decoder_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 37 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053328 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(80) " "Verilog HDL assignment warning at timer_decoder.v(80): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(81) " "Verilog HDL assignment warning at timer_decoder.v(81): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(82) " "Verilog HDL assignment warning at timer_decoder.v(82): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 82 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(83) " "Verilog HDL assignment warning at timer_decoder.v(83): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 83 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(84) " "Verilog HDL assignment warning at timer_decoder.v(84): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(85) " "Verilog HDL assignment warning at timer_decoder.v(85): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718872053329 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
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|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ws2812_circuit circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst " "Elaborating entity \"ws2812_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "ws2812_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053340 ""}
|
||
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|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ws2812_ctrl circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|ws2812_ctrl:ws2812_ctrl_inst " "Elaborating entity \"ws2812_ctrl\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|ws2812_ctrl:ws2812_ctrl_inst\"" { } { { "../rtl/ws2812/ws2812_circuit.v" "ws2812_ctrl_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053349 ""}
|
||
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|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_cfg circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|data_cfg:data_cfg_inst " "Elaborating entity \"data_cfg\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|data_cfg:data_cfg_inst\"" { } { { "../rtl/ws2812/ws2812_circuit.v" "data_cfg_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872053360 ""}
|
||
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|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sa24.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sa24.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sa24 " "Found entity 1: altsyncram_sa24" { } { { "db/altsyncram_sa24.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/altsyncram_sa24.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872057809 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872057809 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rsc " "Found entity 1: mux_rsc" { } { { "db/mux_rsc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/mux_rsc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872058308 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872058308 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_dvf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_dvf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_dvf " "Found entity 1: decode_dvf" { } { { "db/decode_dvf.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/decode_dvf.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872058474 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872058474 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_fgi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_fgi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_fgi " "Found entity 1: cntr_fgi" { } { { "db/cntr_fgi.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_fgi.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872058691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872058691 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_sgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_sgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_sgc " "Found entity 1: cmpr_sgc" { } { { "db/cmpr_sgc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_sgc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872058774 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872058774 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_g9j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_g9j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_g9j " "Found entity 1: cntr_g9j" { } { { "db/cntr_g9j.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_g9j.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872058888 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872058888 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_egi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_egi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_egi " "Found entity 1: cntr_egi" { } { { "db/cntr_egi.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_egi.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872059071 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872059071 ""}
|
||
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_rgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_rgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_rgc " "Found entity 1: cmpr_rgc" { } { { "db/cmpr_rgc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_rgc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872059150 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872059150 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_23j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_23j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_23j " "Found entity 1: cntr_23j" { } { { "db/cntr_23j.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_23j.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872059406 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872059406 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ngc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ngc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ngc " "Found entity 1: cmpr_ngc" { } { { "db/cmpr_ngc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_ngc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872059573 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872059573 ""}
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{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated Signal Tap or debug node instance \"auto_signaltap_0\"" { } { } 0 12033 "Analysis and Synthesis generated Signal Tap or debug node instance \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872060861 ""}
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{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." { } { } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1718872061208 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2024.06.20.16:27:48 Progress: Loading sldbacf2b6c/alt_sld_fab_wrapper_hw.tcl " "2024.06.20.16:27:48 Progress: Loading sldbacf2b6c/alt_sld_fab_wrapper_hw.tcl" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872068468 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872074635 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872075247 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872083745 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872083878 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872084012 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872084208 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872084245 ""}
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{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872084246 ""}
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{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." { } { } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1718872085036 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" { } { { "db/ip/sldbacf2b6c/alt_sld_fab.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085281 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085281 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085385 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085385 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085430 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085430 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085520 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085520 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085640 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085640 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085640 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872085744 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872085744 ""}
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{ "Info" "ILPMS_INFERENCING_SUMMARY" "10 " "Inferred 10 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod1\"" { } { { "../rtl/digit_led/timer.v" "Mod1" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod2\"" { } { { "../rtl/digit_led/timer_decoder.v" "Mod2" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div2\"" { } { { "../rtl/digit_led/timer_decoder.v" "Div2" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Div0\"" { } { { "../rtl/digit_led/timer.v" "Div0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div0\"" { } { { "../rtl/digit_led/timer_decoder.v" "Div0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod0\"" { } { { "../rtl/digit_led/timer_decoder.v" "Mod0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872088940 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872089094 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089094 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089094 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089094 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089094 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872089094 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8bm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8bm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8bm " "Found entity 1: lpm_divide_8bm" { } { { "db/lpm_divide_8bm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_8bm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089193 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089193 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_tlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_tlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_tlh " "Found entity 1: sign_div_unsign_tlh" { } { { "db/sign_div_unsign_tlh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_tlh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089272 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089272 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_e7f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_e7f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_e7f " "Found entity 1: alt_u_div_e7f" { } { { "db/alt_u_div_e7f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_e7f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089337 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089337 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" { } { { "db/add_sub_7pc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_7pc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089490 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089490 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" { } { { "db/add_sub_8pc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_8pc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089591 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089591 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872089667 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 6 " "Parameter \"LPM_WIDTHN\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089667 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089667 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089667 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089667 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872089667 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_k9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_k9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_k9m " "Found entity 1: lpm_divide_k9m" { } { { "db/lpm_divide_k9m.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_k9m.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089756 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089756 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Found entity 1: sign_div_unsign_9kh" { } { { "db/sign_div_unsign_9kh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_9kh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089819 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089819 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_64f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_64f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_64f " "Found entity 1: alt_u_div_64f" { } { { "db/alt_u_div_64f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872089875 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872089875 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872089988 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 6 " "Parameter \"LPM_WIDTHN\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089988 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089988 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089988 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872089988 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872089988 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_hhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hhm " "Found entity 1: lpm_divide_hhm" { } { { "db/lpm_divide_hhm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_hhm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090074 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090074 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872090196 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090196 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 12 " "Parameter \"LPM_WIDTHD\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090196 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090196 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090196 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872090196 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ikm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ikm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ikm " "Found entity 1: lpm_divide_ikm" { } { { "db/lpm_divide_ikm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ikm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090276 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090276 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_anh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_anh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_anh " "Found entity 1: sign_div_unsign_anh" { } { { "db/sign_div_unsign_anh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_anh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090321 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090321 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_8af.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_8af.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_8af " "Found entity 1: alt_u_div_8af" { } { { "db/alt_u_div_8af.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_8af.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090383 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090383 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872090542 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 5 " "Parameter \"LPM_WIDTHN\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090542 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090542 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090542 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090542 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872090542 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ghm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ghm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ghm " "Found entity 1: lpm_divide_ghm" { } { { "db/lpm_divide_ghm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ghm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090602 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090602 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_8kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_8kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_8kh " "Found entity 1: sign_div_unsign_8kh" { } { { "db/sign_div_unsign_8kh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_8kh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090649 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090649 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_44f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_44f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_44f " "Found entity 1: alt_u_div_44f" { } { { "db/alt_u_div_44f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090700 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090700 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872090825 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 5 " "Parameter \"LPM_WIDTHN\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090825 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872090825 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872090825 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_j9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_j9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_j9m " "Found entity 1: lpm_divide_j9m" { } { { "db/lpm_divide_j9m.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_j9m.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872090896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872090896 ""}
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872091054 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091054 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 12 " "Parameter \"LPM_WIDTHD\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091054 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091054 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091054 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872091054 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_lcm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_lcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_lcm " "Found entity 1: lpm_divide_lcm" { } { { "db/lpm_divide_lcm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_lcm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872091127 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872091127 ""}
|
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{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872091355 ""}
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{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 12 " "Parameter \"LPM_WIDTHN\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091355 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872091355 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718872091355 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0jm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_0jm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0jm " "Found entity 1: lpm_divide_0jm" { } { { "db/lpm_divide_0jm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_0jm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872091492 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872091492 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Found entity 1: sign_div_unsign_olh" { } { { "db/sign_div_unsign_olh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_olh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872091563 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872091563 ""}
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_47f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_47f " "Found entity 1: alt_u_div_47f" { } { { "db/alt_u_div_47f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_47f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718872091669 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872091669 ""}
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{ "Info" "IMLS_MLS_DUP_LATCH_INFO_HDR" "" "Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IMLS_MLS_DUP_LATCH_INFO" "circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[5\] circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] " "Duplicate LATCH primitive \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[5\]\" merged with LATCH primitive \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\]\"" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 -1 0 } } } 0 13026 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "Design Software" 0 -1 1718872093041 ""} } { } 0 13025 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "Analysis & Synthesis" 0 -1 1718872093041 ""}
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{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA instruction_reg\[0\] " "Ports D and ENA on the latch are fed by the same signal instruction_reg\[0\]" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 27 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1718872093042 ""} } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1718872093042 ""}
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{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 11 -1 0 } } { "../rtl/beep/pwm_beep.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" 7 -1 0 } } { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 64 -1 0 } } { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 11 -1 0 } } { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 12 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1718872093053 ""}
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{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1718872093053 ""}
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{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led\[7\] VCC " "Pin \"seg_led\[7\]\" is stuck at VCC" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 9 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1718872094159 "|stark_machine|seg_led[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1718872094159 ""}
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{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872094431 ""}
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{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\|lpm_divide_ghm:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\|lpm_divide_ghm:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872096243 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_4_result_int\[0\]~0 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_4_result_int\[0\]~0\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_4_result_int\[0\]~0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 46 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872096243 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872096243 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_64f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872096243 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_4_result_int\[0\]~10 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_4_result_int\[0\]~10\"" { } { { "db/alt_u_div_64f.tdf" "add_sub_4_result_int\[0\]~10" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 46 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718872096243 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod1\|lpm_divide_k9m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_5_result_int\[0\]~0 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_c
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{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg " "Generated suppressed messages file C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872096581 ""}
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{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 133 " "Successfully connected in-system debug instance \"auto_signaltap_0\" to all 133 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" { } { } 0 35024 "Successfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Analysis & Synthesis" 0 -1 1718872098678 ""}
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{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1718872098734 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718872098734 ""}
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{ "Info" "ICUT_CUT_TM_SUMMARY" "2905 " "Implemented 2905 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1718872099279 ""} { "Info" "ICUT_CUT_TM_OPINS" "22 " "Implemented 22 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1718872099279 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2826 " "Implemented 2826 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1718872099279 ""} { "Info" "ICUT_CUT_TM_RAMS" "50 " "Implemented 50 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1718872099279 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1718872099279 ""}
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{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4860 " "Peak virtual memory: 4860 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718872099329 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 20 16:28:19 2024 " "Processing ended: Thu Jun 20 16:28:19 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718872099329 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:01:06 " "Elapsed time: 00:01:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718872099329 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:01:31 " "Total CPU time (on all processors): 00:01:31" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718872099329 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1718872099329 ""}
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