You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
273 lines
162 KiB
Plaintext
273 lines
162 KiB
Plaintext
5 months ago
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1718258380181 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718258380181 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 13 13:59:40 2024 " "Processing started: Thu Jun 13 13:59:40 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718258380181 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258380181 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga " "Command: quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258380196 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1718258380577 ""}
|
||
|
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1718258380577 ""}
|
||
|
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "uart_tx.v(28) " "Verilog HDL warning at uart_tx.v(28): extended using \"x\" or \"z\"" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 28 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1718258389610 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_tx.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_tx " "Found entity 1: uart_tx" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389610 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389610 ""}
|
||
|
|
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "uart_rx.v(96) " "Verilog HDL warning at uart_rx.v(96): extended using \"x\" or \"z\"" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 96 0 0 } } } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "Analysis & Synthesis" 0 -1 1718258389616 ""}
|
||
|
|
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "uart_rx.v(94) " "Verilog HDL information at uart_rx.v(94): always construct contains both blocking and non-blocking assignments" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 94 0 0 } } } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1718258389616 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_rx.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" { { "Info" "ISGN_ENTITY_NAME" "1 uart_rx " "Found entity 1: uart_rx" { } { { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389620 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389620 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/param.v 0 0 " "Found 0 design units, including 0 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/param.v" { } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389621 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit ws2812_ctrl.v(4) " "Verilog HDL Declaration warning at ws2812_ctrl.v(4): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 4 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718258389621 ""}
|
||
|
|
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "bit BIT ws2812_ctrl.v(4) " "Verilog HDL Declaration information at ws2812_ctrl.v(4): object \"bit\" differs only in case from object \"BIT\" in the same scope" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 4 0 0 } } } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1718258389621 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" { { "Info" "ISGN_ENTITY_NAME" "1 ws2812_ctrl " "Found entity 1: ws2812_ctrl" { } { { "../rtl/ws2812/ws2812_ctrl.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389621 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389621 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit ws2812_circuit.v(14) " "Verilog HDL Declaration warning at ws2812_circuit.v(14): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/ws2812_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 14 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718258389621 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 ws2812_circuit " "Found entity 1: ws2812_circuit" { } { { "../rtl/ws2812/ws2812_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389631 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389631 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "bit data_cfg.v(7) " "Verilog HDL Declaration warning at data_cfg.v(7): \"bit\" is SystemVerilog-2005 keyword" { } { { "../rtl/ws2812/data_cfg.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" 7 0 0 } } } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "Analysis & Synthesis" 0 -1 1718258389632 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" { { "Info" "ISGN_ENTITY_NAME" "1 data_cfg " "Found entity 1: data_cfg" { } { { "../rtl/ws2812/data_cfg.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389632 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389632 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer_decoder " "Found entity 1: timer_decoder" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389641 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389641 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 timer " "Found entity 1: timer" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389641 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389641 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 clock_circuit " "Found entity 1: clock_circuit" { } { { "../rtl/digit_led/clock_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389647 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389647 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwm_beep " "Found entity 1: pwm_beep" { } { { "../rtl/beep/pwm_beep.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389651 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389651 ""}
|
||
|
|
{ "Warning" "WVRFX_VERI_LITERAL_TRUNCATED_TO_FIT" "6 freq_select.v(12) " "Verilog HDL Expression warning at freq_select.v(12): truncated literal to match 6 bits" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 12 0 0 } } } 0 10229 "Verilog HDL Expression warning at %2!s!: truncated literal to match %1!d! bits" 0 0 "Analysis & Synthesis" 0 -1 1718258389651 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/freq_select.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/freq_select.v" { { "Info" "ISGN_ENTITY_NAME" "1 freq_select " "Found entity 1: freq_select" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389651 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389651 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 beep_circuit " "Found entity 1: beep_circuit" { } { { "../rtl/beep/beep_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389661 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389661 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/led/led_circuit.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/led/led_circuit.v" { { "Info" "ISGN_ENTITY_NAME" "1 led_circuit " "Found entity 1: led_circuit" { } { { "../rtl/led/led_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389663 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389663 ""}
|
||
|
|
{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_tx.v " "Can't analyze file -- file ../rtl/uart_tx.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718258389663 ""}
|
||
|
|
{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_top.v " "Can't analyze file -- file ../rtl/uart_top.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718258389663 ""}
|
||
|
|
{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/uart_rx.v " "Can't analyze file -- file ../rtl/uart_rx.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718258389671 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/stark_machine.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/stark_machine.v" { { "Info" "ISGN_ENTITY_NAME" "1 stark_machine " "Found entity 1: stark_machine" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389671 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389671 ""}
|
||
|
|
{ "Warning" "WSGN_FILE_IS_MISSING" "../rtl/param.v " "Can't analyze file -- file ../rtl/param.v is missing" { } { } 0 12019 "Can't analyze file -- file %1!s! is missing" 0 0 "Analysis & Synthesis" 0 -1 1718258389680 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/key_filter.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/key_filter.v" { { "Info" "ISGN_ENTITY_NAME" "1 key_filter " "Found entity 1: key_filter" { } { { "../rtl/key_filter.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/key_filter.v" 2 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389682 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/instr_decode.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/instr_decode.v" { { "Info" "ISGN_ENTITY_NAME" "1 instr_decode " "Found entity 1: instr_decode" { } { { "../rtl/instr_decode.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/instr_decode.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389682 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/users/stark-lin/desktop/agi_fpga/hardware/rtl/circuit_arb.v 1 1 " "Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/circuit_arb.v" { { "Info" "ISGN_ENTITY_NAME" "1 circuit_arb " "Found entity 1: circuit_arb" { } { { "../rtl/circuit_arb.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 1 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258389682 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389682 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_TOP" "stark_machine " "Elaborating entity \"stark_machine\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1718258389747 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_rx uart_rx:uart_rx_inst " "Elaborating entity \"uart_rx\" for hierarchy \"uart_rx:uart_rx_inst\"" { } { { "../rtl/stark_machine.v" "uart_rx_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 57 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389769 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "uart_tx uart_tx:uart_tx_inst " "Elaborating entity \"uart_tx\" for hierarchy \"uart_tx:uart_tx_inst\"" { } { { "../rtl/stark_machine.v" "uart_tx_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 66 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389779 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "instr_decode instr_decode:instr_decode_inst " "Elaborating entity \"instr_decode\" for hierarchy \"instr_decode:instr_decode_inst\"" { } { { "../rtl/stark_machine.v" "instr_decode_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 73 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389801 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "circuit_arb circuit_arb:circuit_arb_inst " "Elaborating entity \"circuit_arb\" for hierarchy \"circuit_arb:circuit_arb_inst\"" { } { { "../rtl/stark_machine.v" "circuit_arb_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 87 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389811 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "led_circuit circuit_arb:circuit_arb_inst\|led_circuit:led_circuit_inst " "Elaborating entity \"led_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|led_circuit:led_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "led_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 32 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389822 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 28 led_circuit.v(74) " "Verilog HDL assignment warning at led_circuit.v(74): truncated value with size 32 to match size of target (28)" { } { { "../rtl/led/led_circuit.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v" 74 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389822 "|stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "beep_circuit circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst " "Elaborating entity \"beep_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "beep_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 41 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389839 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "freq_select circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst " "Elaborating entity \"freq_select\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\"" { } { { "../rtl/beep/beep_circuit.v" "freq_select_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 19 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389849 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_INCOMPLETE_CASE_STATEMENT" "freq_select.v(116) " "Verilog HDL Case Statement warning at freq_select.v(116): incomplete case statement has no default case item" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10270 "Verilog HDL Case Statement warning at %1!s!: incomplete case statement has no default case item" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "freq_select.v(116) " "Verilog HDL Case Statement information at freq_select.v(116): all case item expressions in this case statement are onehot" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_ALWAYS_ID_HOLDS_VALUE" "note freq_select.v(116) " "Verilog HDL Always Construct warning at freq_select.v(116): inferring latch(es) for variable \"note\", which holds its previous value in one or more paths through the always construct" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10240 "Verilog HDL Always Construct warning at %2!s!: inferring latch(es) for variable \"%1!s!\", which holds its previous value in one or more paths through the always construct" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[0\] freq_select.v(116) " "Inferred latch for \"note\[0\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[1\] freq_select.v(116) " "Inferred latch for \"note\[1\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[2\] freq_select.v(116) " "Inferred latch for \"note\[2\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[3\] freq_select.v(116) " "Inferred latch for \"note\[3\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[4\] freq_select.v(116) " "Inferred latch for \"note\[4\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "IVRFX_L2_VDB_LATCH_INFERRED" "note\[5\] freq_select.v(116) " "Inferred latch for \"note\[5\]\" at freq_select.v(116)" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 0 0 } } } 0 10041 "Inferred latch for \"%1!s!\" at %2!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258389854 "|stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_beep circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|pwm_beep:pwm_beep_inst " "Elaborating entity \"pwm_beep\" for hierarchy \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|pwm_beep:pwm_beep_inst\"" { } { { "../rtl/beep/beep_circuit.v" "pwm_beep_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389864 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "clock_circuit circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst " "Elaborating entity \"clock_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "clock_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 51 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389870 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst " "Elaborating entity \"timer\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\"" { } { { "../rtl/digit_led/clock_circuit.v" "timer_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 24 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389886 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 5 timer.v(79) " "Verilog HDL assignment warning at timer.v(79): truncated value with size 32 to match size of target (5)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389886 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 timer.v(80) " "Verilog HDL assignment warning at timer.v(80): truncated value with size 32 to match size of target (6)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389886 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 6 timer.v(81) " "Verilog HDL assignment warning at timer.v(81): truncated value with size 32 to match size of target (6)" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389886 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "timer_decoder circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst " "Elaborating entity \"timer_decoder\" for hierarchy \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\"" { } { { "../rtl/digit_led/clock_circuit.v" "timer_decoder_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v" 37 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 ""}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(80) " "Verilog HDL assignment warning at timer_decoder.v(80): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(81) " "Verilog HDL assignment warning at timer_decoder.v(81): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(82) " "Verilog HDL assignment warning at timer_decoder.v(82): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 82 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(83) " "Verilog HDL assignment warning at timer_decoder.v(83): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 83 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(84) " "Verilog HDL assignment warning at timer_decoder.v(84): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 timer_decoder.v(85) " "Verilog HDL assignment warning at timer_decoder.v(85): truncated value with size 32 to match size of target (4)" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 0 0 } } } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1718258389902 "|stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst"}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ws2812_circuit circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst " "Elaborating entity \"ws2812_circuit\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\"" { } { { "../rtl/circuit_arb.v" "ws2812_circuit_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v" 60 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389918 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ws2812_ctrl circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|ws2812_ctrl:ws2812_ctrl_inst " "Elaborating entity \"ws2812_ctrl\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|ws2812_ctrl:ws2812_ctrl_inst\"" { } { { "../rtl/ws2812/ws2812_circuit.v" "ws2812_ctrl_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 27 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389934 ""}
|
||
|
|
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "data_cfg circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|data_cfg:data_cfg_inst " "Elaborating entity \"data_cfg\" for hierarchy \"circuit_arb:circuit_arb_inst\|ws2812_circuit:ws2812_circuit_inst\|data_cfg:data_cfg_inst\"" { } { { "../rtl/ws2812/ws2812_circuit.v" "data_cfg_inst" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v" 34 0 0 } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258389949 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_sa24.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_sa24.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_sa24 " "Found entity 1: altsyncram_sa24" { } { { "db/altsyncram_sa24.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/altsyncram_sa24.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258391896 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258391896 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_rsc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_rsc " "Found entity 1: mux_rsc" { } { { "db/mux_rsc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/mux_rsc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392097 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392097 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/decode_dvf.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/decode_dvf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 decode_dvf " "Found entity 1: decode_dvf" { } { { "db/decode_dvf.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/decode_dvf.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392188 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392188 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_fgi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_fgi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_fgi " "Found entity 1: cntr_fgi" { } { { "db/cntr_fgi.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_fgi.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392324 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392324 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_sgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_sgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_sgc " "Found entity 1: cmpr_sgc" { } { { "db/cmpr_sgc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_sgc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392394 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392394 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_g9j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_g9j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_g9j " "Found entity 1: cntr_g9j" { } { { "db/cntr_g9j.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_g9j.tdf" 25 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392487 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392487 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_egi.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_egi.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_egi " "Found entity 1: cntr_egi" { } { { "db/cntr_egi.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_egi.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392622 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392622 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_rgc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_rgc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_rgc " "Found entity 1: cmpr_rgc" { } { { "db/cmpr_rgc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_rgc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392666 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392666 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_23j.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_23j.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_23j " "Found entity 1: cntr_23j" { } { { "db/cntr_23j.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_23j.tdf" 27 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392752 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392752 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_ngc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_ngc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_ngc " "Found entity 1: cmpr_ngc" { } { { "db/cmpr_ngc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_ngc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258392805 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258392805 ""}
|
||
|
|
{ "Info" "ISGN_AE_SUCCESSFUL" "auto_signaltap_0 " "Analysis and Synthesis generated Signal Tap or debug node instance \"auto_signaltap_0\"" { } { } 0 12033 "Analysis and Synthesis generated Signal Tap or debug node instance \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258393268 ""}
|
||
|
|
{ "Info" "ISCI_START_SUPER_FABRIC_GEN" "alt_sld_fab " "Starting IP generation for the debug fabric: alt_sld_fab." { } { } 0 11170 "Starting IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1718258393394 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "2024.06.13.13:59:57 Progress: Loading sldbacf2b6c/alt_sld_fab_wrapper_hw.tcl " "2024.06.13.13:59:57 Progress: Loading sldbacf2b6c/alt_sld_fab_wrapper_hw.tcl" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258397470 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG " "Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258400547 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH " "Alt_sld_fab: Generating alt_sld_fab \"alt_sld_fab\" for QUARTUS_SYNTH" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258400674 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\" " "Alt_sld_fab: \"alt_sld_fab\" instantiated alt_sld_fab \"alt_sld_fab\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404508 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\" " "Presplit: \"alt_sld_fab\" instantiated altera_super_splitter \"presplit\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404598 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\" " "Splitter: \"alt_sld_fab\" instantiated altera_sld_splitter \"splitter\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404684 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\" " "Sldfabric: \"alt_sld_fab\" instantiated altera_sld_jtag_hub \"sldfabric\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404811 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\" " "Ident: \"alt_sld_fab\" instantiated altera_connection_identification_hub \"ident\"" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404815 ""}
|
||
|
|
{ "Info" "ISCI_EXT_PROC_INFO_MSG" "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files " "Alt_sld_fab: Done \"alt_sld_fab\" with 6 modules, 6 files" { } { } 0 11172 "%1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258404815 ""}
|
||
|
|
{ "Info" "ISCI_END_SUPER_FABRIC_GEN" "alt_sld_fab " "Finished IP generation for the debug fabric: alt_sld_fab." { } { } 0 11171 "Finished IP generation for the debug fabric: %1!s!." 0 0 "Analysis & Synthesis" 0 -1 1718258405511 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab " "Found entity 1: alt_sld_fab" { } { { "db/ip/sldbacf2b6c/alt_sld_fab.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405708 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258405708 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab " "Found entity 1: alt_sld_fab_alt_sld_fab" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v" 9 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405788 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258405788 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_ident " "Found entity 1: alt_sld_fab_alt_sld_fab_ident" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv" 33 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405804 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258405804 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_presplit " "Found entity 1: alt_sld_fab_alt_sld_fab_presplit" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405868 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258405868 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd 2 1 " "Found 2 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric-rtl " "Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 102 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405952 ""} { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_sldfabric " "Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd" 11 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258405952 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258405952 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv 1 1 " "Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_sld_fab_alt_sld_fab_splitter " "Found entity 1: alt_sld_fab_alt_sld_fab_splitter" { } { { "db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv" 3 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258406016 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258406016 ""}
|
||
|
|
{ "Info" "ILPMS_INFERENCING_SUMMARY" "10 " "Inferred 10 megafunctions from design logic" { { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod1 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod1\"" { } { { "../rtl/digit_led/timer.v" "Mod1" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod2\"" { } { { "../rtl/digit_led/timer_decoder.v" "Mod2" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div2 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div2\"" { } { { "../rtl/digit_led/timer_decoder.v" "Div2" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Div0\"" { } { { "../rtl/digit_led/timer.v" "Div0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Div0\"" { } { { "../rtl/digit_led/timer_decoder.v" "Div0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|Mod0\"" { } { { "../rtl/digit_led/timer_decoder.v" "Mod0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 278004 "Inferred divider/modulo megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258407670 ""} { "Info" "ILPMS_LPM_DIVIDE_INFERRED" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|Mod0 lpm_divide " "Inferred divider/modulo megafunction (\"lpm_divide\") from the following logic: \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258407734 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258407734 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258407734 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258407734 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258407734 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 81 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258407734 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_8bm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_8bm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_8bm " "Found entity 1: lpm_divide_8bm" { } { { "db/lpm_divide_8bm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_8bm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258407787 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258407787 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_tlh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_tlh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_tlh " "Found entity 1: sign_div_unsign_tlh" { } { { "db/sign_div_unsign_tlh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_tlh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258407823 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258407823 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_e7f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_e7f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_e7f " "Found entity 1: alt_u_div_e7f" { } { { "db/alt_u_div_e7f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_e7f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258407866 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258407866 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_7pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_7pc " "Found entity 1: add_sub_7pc" { } { { "db/add_sub_7pc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_7pc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258407956 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258407956 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_8pc.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_8pc " "Found entity 1: add_sub_8pc" { } { { "db/add_sub_8pc.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_8pc.tdf" 22 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408025 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408025 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408061 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 6 " "Parameter \"LPM_WIDTHN\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408061 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408061 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 85 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408061 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_k9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_k9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_k9m " "Found entity 1: lpm_divide_k9m" { } { { "db/lpm_divide_k9m.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_k9m.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408105 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408105 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_9kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_9kh " "Found entity 1: sign_div_unsign_9kh" { } { { "db/sign_div_unsign_9kh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_9kh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408147 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408147 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_64f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_64f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_64f " "Found entity 1: alt_u_div_64f" { } { { "db/alt_u_div_64f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408173 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408173 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408241 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div2\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 6 " "Parameter \"LPM_WIDTHN\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408241 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408241 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 84 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408241 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_hhm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_hhm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_hhm " "Found entity 1: lpm_divide_hhm" { } { { "db/lpm_divide_hhm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_hhm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408295 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408295 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408379 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 12 " "Parameter \"LPM_WIDTHD\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408379 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408379 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 79 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408379 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ikm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ikm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ikm " "Found entity 1: lpm_divide_ikm" { } { { "db/lpm_divide_ikm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ikm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408432 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408432 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_anh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_anh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_anh " "Found entity 1: sign_div_unsign_anh" { } { { "db/sign_div_unsign_anh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_anh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408464 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408464 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_8af.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_8af.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_8af " "Found entity 1: alt_u_div_8af" { } { { "db/alt_u_div_8af.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_8af.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408512 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408512 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408600 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 5 " "Parameter \"LPM_WIDTHN\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408600 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408600 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408600 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408600 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408600 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_ghm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_ghm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_ghm " "Found entity 1: lpm_divide_ghm" { } { { "db/lpm_divide_ghm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ghm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408654 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408654 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_8kh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_8kh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_8kh " "Found entity 1: sign_div_unsign_8kh" { } { { "db/sign_div_unsign_8kh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_8kh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408691 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408691 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_44f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_44f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_44f " "Found entity 1: alt_u_div_44f" { } { { "db/alt_u_div_44f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408723 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408723 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\"" { } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408801 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 5 " "Parameter \"LPM_WIDTHN\" = \"5\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408801 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 4 " "Parameter \"LPM_WIDTHD\" = \"4\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408801 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408801 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408801 ""} } { { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 81 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408801 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_j9m.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_j9m.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_j9m " "Found entity 1: lpm_divide_j9m" { } { { "db/lpm_divide_j9m.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_j9m.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258408859 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258408859 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258408954 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Mod0\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 17 " "Parameter \"LPM_WIDTHN\" = \"17\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408954 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 12 " "Parameter \"LPM_WIDTHD\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408954 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408954 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258408954 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258408954 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_lcm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_lcm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_lcm " "Found entity 1: lpm_divide_lcm" { } { { "db/lpm_divide_lcm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_lcm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258409008 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258409008 ""}
|
||
|
|
{ "Info" "ISGN_ELABORATION_HEADER" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1 " "Elaborated megafunction instantiation \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1\"" { } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258409081 ""}
|
||
|
|
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1 " "Instantiated megafunction \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|lpm_divide:Div1\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHN 12 " "Parameter \"LPM_WIDTHN\" = \"12\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258409081 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_WIDTHD 6 " "Parameter \"LPM_WIDTHD\" = \"6\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258409081 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_NREPRESENTATION UNSIGNED " "Parameter \"LPM_NREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258409081 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "LPM_DREPRESENTATION UNSIGNED " "Parameter \"LPM_DREPRESENTATION\" = \"UNSIGNED\"" { } { } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258409081 ""} } { { "../rtl/digit_led/timer.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v" 80 -1 0 } } } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1718258409081 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_0jm.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/lpm_divide_0jm.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_0jm " "Found entity 1: lpm_divide_0jm" { } { { "db/lpm_divide_0jm.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_0jm.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258409134 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258409134 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_olh.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_olh " "Found entity 1: sign_div_unsign_olh" { } { { "db/sign_div_unsign_olh.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_olh.tdf" 24 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258409181 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258409181 ""}
|
||
|
|
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_47f.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_47f " "Found entity 1: alt_u_div_47f" { } { { "db/alt_u_div_47f.tdf" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_47f.tdf" 26 1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1718258409221 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258409221 ""}
|
||
|
|
{ "Info" "IMLS_MLS_DUP_LATCH_INFO_HDR" "" "Duplicate LATCH primitives merged into single LATCH primitive" { { "Info" "IMLS_MLS_DUP_LATCH_INFO" "circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[5\] circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] " "Duplicate LATCH primitive \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[5\]\" merged with LATCH primitive \"circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\]\"" { } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 -1 0 } } } 0 13026 "Duplicate LATCH primitive \"%1!s!\" merged with LATCH primitive \"%2!s!\"" 0 0 "Design Software" 0 -1 1718258409794 ""} } { } 0 13025 "Duplicate LATCH primitives merged into single LATCH primitive" 0 0 "Analysis & Synthesis" 0 -1 1718258409794 ""}
|
||
|
|
{ "Warning" "WMLS_MLS_UNSAFE_LATCH_HDR" "circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] has unsafe behavior" { { "Warning" "WMLS_MLS_UNSAFE_LATCH_SUB" "D ENA instruction_reg\[0\] " "Ports D and ENA on the latch are fed by the same signal instruction_reg\[0\]" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 27 -1 0 } } } 0 13013 "Ports %1!s! and %2!s! on the latch are fed by the same signal %3!s!" 0 0 "Design Software" 0 -1 1718258409795 ""} } { { "../rtl/beep/freq_select.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v" 116 -1 0 } } } 0 13012 "Latch %1!s! has unsafe behavior" 0 0 "Analysis & Synthesis" 0 -1 1718258409795 ""}
|
||
|
|
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" { } { { "../rtl/uart/uart_tx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v" 11 -1 0 } } { "../rtl/beep/pwm_beep.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v" 7 -1 0 } } { "../rtl/digit_led/timer_decoder.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v" 64 -1 0 } } { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 11 -1 0 } } { "../rtl/uart/uart_rx.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v" 12 -1 0 } } } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1718258409799 ""}
|
||
|
|
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" { } { } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1718258409799 ""}
|
||
|
|
{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "seg_led\[7\] VCC " "Pin \"seg_led\[7\]\" is stuck at VCC" { } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 9 -1 0 } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Design Software" 0 -1 1718258410616 "|stark_machine|seg_led[7]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Analysis & Synthesis" 0 -1 1718258410616 ""}
|
||
|
|
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING_ON_PARTITION" "Top " "Timing-Driven Synthesis is running on partition \"Top\"" { } { } 0 286031 "Timing-Driven Synthesis is running on partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258410724 ""}
|
||
|
|
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\|lpm_divide_ghm:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div0\|lpm_divide_ghm:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258412251 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_4_result_int\[0\]~0 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_4_result_int\[0\]~0\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_4_result_int\[0\]~0" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 46 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258412251 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod0\|lpm_divide_j9m:auto_generated\|sign_div_unsign_8kh:divider\|alt_u_div_44f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_44f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258412251 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_3_result_int\[0\]~8 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_3_result_int\[0\]~8\"" { } { { "db/alt_u_div_64f.tdf" "add_sub_3_result_int\[0\]~8" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 41 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258412251 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_4_result_int\[0\]~10 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Div1\|lpm_divide_hhm:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_4_result_int\[0\]~10\"" { } { { "db/alt_u_div_64f.tdf" "add_sub_4_result_int\[0\]~10" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf" 46 22 0 } } } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1718258412251 ""} { "Info" "ISCL_SCL_CELL_NAME" "circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer_decoder:timer_decoder_inst\|lpm_divide:Mod1\|lpm_divide_k9m:auto_generated\|sign_div_unsign_9kh:divider\|alt_u_div_64f:divider\|add_sub_5_result_int\[0\]~0 " "Logic cell \"circuit_arb:circuit_arb_inst\|clock_circuit:clock_c
|
||
|
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg " "Generated suppressed messages file C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258412474 ""}
|
||
|
|
{ "Info" "IAMERGE_SLD_INSTANCE_WITH_FULL_CONNECTIONS" "auto_signaltap_0 133 " "Successfully connected in-system debug instance \"auto_signaltap_0\" to all 133 required data inputs, trigger inputs, acquisition clocks, and dynamic pins" { } { } 0 35024 "Successfully connected in-system debug instance \"%1!s!\" to all %2!d! required data inputs, trigger inputs, acquisition clocks, and dynamic pins" 0 0 "Analysis & Synthesis" 0 -1 1718258413806 ""}
|
||
|
|
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1718258413853 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1718258413853 ""}
|
||
|
|
{ "Info" "ICUT_CUT_TM_SUMMARY" "2904 " "Implemented 2904 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "6 " "Implemented 6 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1718258414167 ""} { "Info" "ICUT_CUT_TM_OPINS" "22 " "Implemented 22 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1718258414167 ""} { "Info" "ICUT_CUT_TM_LCELLS" "2825 " "Implemented 2825 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1718258414167 ""} { "Info" "ICUT_CUT_TM_RAMS" "50 " "Implemented 50 RAM segments" { } { } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1718258414167 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1718258414167 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 25 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4871 " "Peak virtual memory: 4871 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718258414219 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 13 14:00:14 2024 " "Processing ended: Thu Jun 13 14:00:14 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718258414219 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:34 " "Elapsed time: 00:00:34" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718258414219 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:27 " "Total CPU time (on all processors): 00:00:27" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718258414219 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1718258414219 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Analysis & Synthesis" 0 -1 1718258415433 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus Prime " "Running Quartus Prime Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718258415445 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 13 14:00:15 2024 " "Processing started: Thu Jun 13 14:00:15 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718258415445 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Fitter" 0 -1 1718258415445 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga " "Command: quartus_fit --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Fitter" 0 -1 1718258415445 ""}
|
||
|
|
{ "Info" "0" "" "qfit2_default_script.tcl version: #1" { } { } 0 0 "qfit2_default_script.tcl version: #1" 0 0 "Fitter" 0 0 1718258415560 ""}
|
||
|
|
{ "Info" "0" "" "Project = agi_fpga" { } { } 0 0 "Project = agi_fpga" 0 0 "Fitter" 0 0 1718258415560 ""}
|
||
|
|
{ "Info" "0" "" "Revision = agi_fpga" { } { } 0 0 "Revision = agi_fpga" 0 0 "Fitter" 0 0 1718258415560 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Fitter" 0 -1 1718258415698 ""}
|
||
|
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Fitter" 0 -1 1718258415698 ""}
|
||
|
|
{ "Info" "IMPP_MPP_USER_DEVICE" "agi_fpga EP4CE6F17C8 " "Selected device EP4CE6F17C8 for design \"agi_fpga\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1718258415730 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1718258415779 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1718258415779 ""}
|
||
|
|
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1718258415937 ""}
|
||
|
|
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1718258415947 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE10F17C8 " "Device EP4CE10F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1718258416113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE15F17C8 " "Device EP4CE15F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1718258416113 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP4CE22F17C8 " "Device EP4CE22F17C8 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Design Software" 0 -1 1718258416113 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1718258416113 ""}
|
||
|
|
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "4 " "Fitter converted 4 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_ASDO_DATA1~ C1 " "Pin ~ALTERA_ASDO_DATA1~ is reserved at location C1" { } { { "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_ASDO_DATA1~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7273 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1718258416117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_FLASH_nCE_nCSO~ D2 " "Pin ~ALTERA_FLASH_nCE_nCSO~ is reserved at location D2" { } { { "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_FLASH_nCE_nCSO~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7275 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1718258416117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DCLK~ H1 " "Pin ~ALTERA_DCLK~ is reserved at location H1" { } { { "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DCLK~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7277 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1718258416117 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ALTERA_DATA0~ H2 " "Pin ~ALTERA_DATA0~ is reserved at location H2" { } { { "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "d:/intelfpga_lite/18.1/quartus/bin64/pin_planner.ppl" { ~ALTERA_DATA0~ } } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7279 14177 15141 0 0 "" 0 "" "" } } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Design Software" 0 -1 1718258416117 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1718258416117 ""}
|
||
|
|
{ "Warning" "WCUT_CUT_ATOM_PINS_WITH_INCOMPLETE_IO_ASSIGNMENTS" "" "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" { } { } 0 15714 "Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details" 0 0 "Fitter" 0 -1 1718258416128 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." { } { } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1718258416159 ""}
|
||
|
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Fitter" 0 -1 1718258416951 ""}
|
||
|
|
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718258416951 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718258416951 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1718258416951 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Fitter" 0 -1 1718258416951 ""}
|
||
|
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "agi_fpga.sdc " "Synopsys Design Constraints File file not found: 'agi_fpga.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1718258416971 ""}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258416982 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1718258416982 "|stark_machine|sys_clk"}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258416982 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Fitter" 0 -1 1718258416982 "|stark_machine|byte_num[0]"}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258417002 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258417002 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Fitter" 0 -1 1718258417002 ""}
|
||
|
|
{ "Info" "ISTA_USER_TDC_OPTIMIZATION_GOALS" "" "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 332129 "Detected timing requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "Fitter" 0 -1 1718258417002 ""}
|
||
|
|
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 1 clocks " "Found 1 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" " Period Clock Name " " Period Clock Name" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1718258417002 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1718258417002 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" " 100.000 altera_reserved_tck " " 100.000 altera_reserved_tck" { } { } 0 332111 "%1!s!" 0 0 "Design Software" 0 -1 1718258417002 ""} } { } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1718258417002 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n)) " "Automatically promoted node sys_clk~input (placed in PIN E1 (CLK1, DIFFCLK_0n))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 2 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7260 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1718258417222 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "altera_internal_jtag~TCKUTAP " "Automatically promoted node altera_internal_jtag~TCKUTAP " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} } { { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 3407 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1718258417222 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sys_rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p)) " "Automatically promoted node sys_rst_n~input (placed in PIN E15 (CLK4, DIFFCLK_2p))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G9 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G9" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} } { { "../rtl/stark_machine.v" "" { Text "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v" 3 0 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 7261 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1718258417222 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all " "Automatically promoted node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|reset_all " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\]~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_buffer_manager:sld_buffer_manager_inst\|last_buffer_write_address_sig\[0\]~0" { } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 356 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 5647 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0 " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset~0" { } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 638 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 5671 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset " "Destination node sld_signaltap:auto_signaltap_0\|sld_signaltap_impl:sld_signaltap_body\|sld_signaltap_implb:sld_signaltap_body\|sld_offload_buffer_mgr:\\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst\|acq_buf_read_reset" { } { { "sld_buffer_manager.vhd" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd" 638 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 4013 14177 15141 0 0 "" 0 "" "" } } } } } 0 176357 "Destination node %1!s!" 0 0 "Design Software" 0 -1 1718258417222 ""} } { } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Design Software" 0 -1 1718258417222 ""} } { { "sld_signaltap_impl.vhd" "" { Text "d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd" 882 -1 0 } } { "temporary_test_loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 0 { 0 ""} 0 4776 14177 15141 0 0 "" 0 "" "" } } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1718258417222 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1718258417634 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1718258417634 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1718258417634 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1718258417634 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1718258417634 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1718258417650 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1718258417650 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1718258417650 ""}
|
||
|
|
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1718258417731 ""}
|
||
|
|
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Design Software" 0 -1 1718258417731 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1718258417731 ""}
|
||
|
|
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:01 " "Fitter preparation operations ending: elapsed time is 00:00:01" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1718258417797 ""}
|
||
|
|
{ "Info" "IVPR20K_VPR_FAMILY_APL_ERROR" "" "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." { } { } 0 14896 "Fitter has disabled Advanced Physical Optimization because it is not supported for the current family." 0 0 "Fitter" 0 -1 1718258417808 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1718258418398 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:01 " "Fitter placement preparation operations ending: elapsed time is 00:00:01" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1718258419010 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1718258419046 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1718258419809 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1718258419809 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1718258420322 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "4 " "Router estimated average interconnect usage is 4% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "10 X11_Y12 X22_Y24 " "Router estimated peak interconnect usage is 10% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24" { } { { "loc" "" { Generic "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/" { { 1 { 0 "Router estimated peak interconnect usage is 10% of the available device resources in the region that extends from location X11_Y12 to location X22_Y24"} { { 12 { 0 ""} 11 12 12 13 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Design Software" 0 -1 1718258421381 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1718258421381 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Design Software" 0 -1 1718258421570 ""} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Optimizations that may affect the design's timing were skipped" { } { } 0 170200 "Optimizations that may affect the design's timing were skipped" 0 0 "Design Software" 0 -1 1718258421570 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1718258421570 ""}
|
||
|
|
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1718258421574 ""}
|
||
|
|
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "the Fitter 0.47 " "Total time spent on timing analysis during the Fitter is 0.47 seconds." { } { } 0 11888 "Total time spent on timing analysis during %1!s! is %2!s! seconds." 0 0 "Fitter" 0 -1 1718258421786 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1718258421818 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1718258422222 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1718258422222 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1718258422700 ""}
|
||
|
|
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:02 " "Fitter post-fit operations ending: elapsed time is 00:00:02" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1718258423333 ""}
|
||
|
|
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.fit.smsg " "Generated suppressed messages file C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1718258423775 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 10 s Quartus Prime " "Quartus Prime Fitter was successful. 0 errors, 10 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "5523 " "Peak virtual memory: 5523 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718258424865 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 13 14:00:24 2024 " "Processing ended: Thu Jun 13 14:00:24 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718258424865 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Elapsed time: 00:00:09" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718258424865 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:07 " "Total CPU time (on all processors): 00:00:07" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718258424865 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1718258424865 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Fitter" 0 -1 1718258426076 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus Prime " "Running Quartus Prime Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718258426076 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 13 14:00:25 2024 " "Processing started: Thu Jun 13 14:00:25 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718258426076 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1718258426076 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga " "Command: quartus_asm --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1718258426076 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Assembler" 0 -1 1718258426441 ""}
|
||
|
|
{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1718258427340 ""}
|
||
|
|
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1718258427367 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 1 Quartus Prime " "Quartus Prime Assembler was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4681 " "Peak virtual memory: 4681 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718258427582 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 13 14:00:27 2024 " "Processing ended: Thu Jun 13 14:00:27 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718258427582 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718258427582 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718258427582 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1718258427582 ""}
|
||
|
|
{ "Info" "IFLOW_DISABLED_MODULE" "Power Analyzer FLOW_ENABLE_POWER_ANALYZER " "Skipped module Power Analyzer due to the assignment FLOW_ENABLE_POWER_ANALYZER" { } { } 0 293026 "Skipped module %1!s! due to the assignment %2!s!" 0 0 "Assembler" 0 -1 1718258428191 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Assembler" 0 -1 1718258428756 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer Quartus Prime " "Running Quartus Prime Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718258428766 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 13 14:00:28 2024 " "Processing started: Thu Jun 13 14:00:28 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718258428766 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Timing Analyzer" 0 -1 1718258428766 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta agi_fpga -c agi_fpga " "Command: quartus_sta agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "Timing Analyzer" 0 -1 1718258428766 ""}
|
||
|
|
{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Timing Analyzer" 0 0 1718258428862 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Timing Analyzer" 0 -1 1718258429180 ""}
|
||
|
|
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" { } { } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Timing Analyzer" 0 -1 1718258429180 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429234 ""}
|
||
|
|
{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429234 ""}
|
||
|
|
{ "Warning" "WTDB_ANALYZE_COMB_LATCHES" "1 " "The Timing Analyzer is analyzing 1 combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." { } { } 0 335093 "The Timing Analyzer is analyzing %1!d! combinational loops as latches. For more details, run the Check Timing command in the Timing Analyzer or view the \"User-Specified and Inferred Latches\" table in the Analysis & Synthesis report." 0 0 "Timing Analyzer" 0 -1 1718258429456 ""}
|
||
|
|
{ "Info" "ISTA_SDC_STATEMENT_PARENT" "" "Evaluating HDL-embedded SDC commands" { { "Info" "ISTA_SDC_STATEMENT_ENTITY" "sld_hub " "Entity sld_hub" { { "Info" "ISTA_SDC_STATEMENT_EVAL" "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " "create_clock -name altera_reserved_tck \[get_ports \{altera_reserved_tck\}\] -period 10MHz " { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718258429552 ""} { "Info" "ISTA_SDC_STATEMENT_EVAL" "set_clock_groups -asynchronous -group \{altera_reserved_tck\} " "set_clock_groups -asynchronous -group \{altera_reserved_tck\}" { } { } 0 332166 "%1!s!" 0 0 "Design Software" 0 -1 1718258429552 ""} } { } 0 332165 "Entity %1!s!" 0 0 "Design Software" 0 -1 1718258429552 ""} } { } 0 332164 "Evaluating HDL-embedded SDC commands" 0 0 "Timing Analyzer" 0 -1 1718258429552 ""}
|
||
|
|
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "agi_fpga.sdc " "Synopsys Design Constraints File file not found: 'agi_fpga.sdc'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Timing Analyzer" 0 -1 1718258429567 ""}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258429579 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258429579 "|stark_machine|sys_clk"}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258429579 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258429579 "|stark_machine|byte_num[0]"}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258429583 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258429583 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718258429583 ""}
|
||
|
|
{ "Info" "0" "" "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMING_ANALYZER_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Timing Analyzer" 0 0 1718258429594 ""}
|
||
|
|
{ "Info" "0" "" "Analyzing Slow 1200mV 85C Model" { } { } 0 0 "Analyzing Slow 1200mV 85C Model" 0 0 "Timing Analyzer" 0 0 1718258429604 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 43.573 " "Worst-case setup slack is 43.573" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429642 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 43.573 0.000 altera_reserved_tck " " 43.573 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429642 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429642 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.452 " "Worst-case hold slack is 0.452" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.452 0.000 altera_reserved_tck " " 0.452 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429646 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 95.314 " "Worst-case recovery slack is 95.314" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 95.314 0.000 altera_reserved_tck " " 95.314 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429646 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429646 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.610 " "Worst-case removal slack is 1.610" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.610 0.000 altera_reserved_tck " " 1.610 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429658 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.459 " "Worst-case minimum pulse width slack is 49.459" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.459 0.000 altera_reserved_tck " " 49.459 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258429658 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258429658 ""}
|
||
|
|
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 342.288 ns " "Worst Case Available Settling Time: 342.288 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258429721 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718258429721 ""}
|
||
|
|
{ "Info" "0" "" "Analyzing Slow 1200mV 0C Model" { } { } 0 0 "Analyzing Slow 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1718258429732 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_STARTED" "" "Started post-fitting delay annotation" { } { } 0 334003 "Started post-fitting delay annotation" 0 0 "Timing Analyzer" 0 -1 1718258429764 ""}
|
||
|
|
{ "Info" "ITAPI_TAPI_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 334004 "Delay annotation completed successfully" 0 0 "Timing Analyzer" 0 -1 1718258430347 ""}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258430581 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258430581 "|stark_machine|sys_clk"}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258430581 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258430581 "|stark_machine|byte_num[0]"}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258430581 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258430581 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718258430581 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 44.018 " "Worst-case setup slack is 44.018" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 44.018 0.000 altera_reserved_tck " " 44.018 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430613 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.400 " "Worst-case hold slack is 0.400" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.400 0.000 altera_reserved_tck " " 0.400 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430613 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430613 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 95.548 " "Worst-case recovery slack is 95.548" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430629 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430629 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 95.548 0.000 altera_reserved_tck " " 95.548 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430629 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430629 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 1.444 " "Worst-case removal slack is 1.444" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 1.444 0.000 altera_reserved_tck " " 1.444 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430633 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.315 " "Worst-case minimum pulse width slack is 49.315" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.315 0.000 altera_reserved_tck " " 49.315 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430633 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430633 ""}
|
||
|
|
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 342.907 ns " "Worst Case Available Settling Time: 342.907 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258430697 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718258430697 ""}
|
||
|
|
{ "Info" "0" "" "Analyzing Fast 1200mV 0C Model" { } { } 0 0 "Analyzing Fast 1200mV 0C Model" 0 0 "Timing Analyzer" 0 0 1718258430708 ""}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "sys_clk " "Node: sys_clk was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] sys_clk " "Register circuit_arb:circuit_arb_inst\|clock_circuit:clock_circuit_inst\|timer:timer_inst\|cnt_day\[0\] is being clocked by sys_clk" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258430932 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258430932 "|stark_machine|sys_clk"}
|
||
|
|
{ "Warning" "WSTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT" "byte_num\[0\] " "Node: byte_num\[0\] was determined to be a clock but was found without an associated clock assignment." { { "Info" "ISTA_NODE_FOUND_WITHOUT_CLOCK_ASSIGNMENT_DETAILS" "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] byte_num\[0\] " "Latch circuit_arb:circuit_arb_inst\|beep_circuit:beep_circuit_inst\|freq_select:freq_select_inst\|note\[1\] is being clocked by byte_num\[0\]" { } { } 0 13166 "%1!s! %2!s! is being clocked by %3!s!" 0 0 "Design Software" 0 -1 1718258430932 ""} } { } 0 332060 "Node: %1!s! was determined to be a clock but was found without an associated clock assignment." 0 0 "Timing Analyzer" 0 -1 1718258430932 "|stark_machine|byte_num[0]"}
|
||
|
|
{ "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_PARENT" "" "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." { { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Rise) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Rise) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258430946 ""} { "Critical Warning" "WSTA_NO_UNCERTAINTY_WAS_SET_CHILD" "altera_reserved_tck (Rise) altera_reserved_tck (Fall) setup and hold " "From altera_reserved_tck (Rise) to altera_reserved_tck (Fall) (setup and hold)" { } { } 1 332169 "From %1!s! to %2!s! (%3!s!)" 0 0 "Design Software" 0 -1 1718258430946 ""} } { } 1 332168 "The following clock transfers have no clock uncertainty assignment. For more accurate results, apply clock uncertainty assignments or use the derive_clock_uncertainty command." 0 0 "Timing Analyzer" 0 -1 1718258430946 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "setup 47.318 " "Worst-case setup slack is 47.318" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430962 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 47.318 0.000 altera_reserved_tck " " 47.318 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430962 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430962 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.186 " "Worst-case hold slack is 0.186" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430967 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430967 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.186 0.000 altera_reserved_tck " " 0.186 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430967 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430967 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "recovery 97.830 " "Worst-case recovery slack is 97.830" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430978 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 97.830 0.000 altera_reserved_tck " " 97.830 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430978 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430978 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "removal 0.673 " "Worst-case removal slack is 0.673" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430988 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.673 0.000 altera_reserved_tck " " 0.673 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430988 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430988 ""}
|
||
|
|
{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width 49.449 " "Worst-case minimum pulse width slack is 49.449" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= =================== ===================== " "========= =================== =====================" { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430994 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 49.449 0.000 altera_reserved_tck " " 49.449 0.000 altera_reserved_tck " { } { } 0 332119 "%1!s!" 0 0 "Design Software" 0 -1 1718258430994 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Timing Analyzer" 0 -1 1718258430994 ""}
|
||
|
|
{ "Info" "ISTA_REPORT_METASTABILITY_INFO" "Report Metastability: Found 2 synchronizer chains. " "Report Metastability: Found 2 synchronizer chains." { { "Info" "ISTA_REPORT_METASTABILITY_INFO" "The design MTBF is not calculated because there are no specified synchronizers in the design. " "The design MTBF is not calculated because there are no specified synchronizers in the design." { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Number of Synchronizer Chains Found: 2 " "Number of Synchronizer Chains Found: 2" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Shortest Synchronizer Chain: 4 Registers " "Shortest Synchronizer Chain: 4 Registers" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000 " "Fraction of Chains for which MTBFs Could Not be Calculated: 1.000" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" "Worst Case Available Settling Time: 346.943 ns " "Worst Case Available Settling Time: 346.943 ns" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} { "Info" "ISTA_REPORT_METASTABILITY_INFO" " " "" { } { } 0 332114 "%1!s!" 0 0 "Design Software" 0 -1 1718258431073 ""} } { } 0 332114 "%1!s!" 0 0 "Timing Analyzer" 0 -1 1718258431073 ""}
|
||
|
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1718258431537 ""}
|
||
|
|
{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Timing Analyzer" 0 -1 1718258431553 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 18 s Quartus Prime " "Quartus Prime Timing Analyzer was successful. 0 errors, 18 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4785 " "Peak virtual memory: 4785 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718258431679 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 13 14:00:31 2024 " "Processing ended: Thu Jun 13 14:00:31 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718258431679 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718258431679 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718258431679 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Timing Analyzer" 0 -1 1718258431679 ""}
|
||
|
|
{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Timing Analyzer" 0 -1 1718258432911 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus Prime " "Running Quartus Prime EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" { } { } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1718258432917 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Jun 13 14:00:32 2024 " "Processing started: Thu Jun 13 14:00:32 2024" { } { } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1718258432917 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1718258432917 ""}
|
||
|
|
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga " "Command: quartus_eda --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga" { } { } 0 0 "Command: %1!s!" 0 0 "EDA Netlist Writer" 0 -1 1718258432917 ""}
|
||
|
|
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." { } { } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "EDA Netlist Writer" 0 -1 1718258433379 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_8_1200mv_85c_slow.vo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_8_1200mv_85c_slow.vo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258434512 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_8_1200mv_0c_slow.vo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_8_1200mv_0c_slow.vo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258434833 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_min_1200mv_0c_fast.vo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_min_1200mv_0c_fast.vo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258435134 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga.vo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga.vo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258435424 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_8_1200mv_85c_v_slow.sdo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_8_1200mv_85c_v_slow.sdo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258435690 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_8_1200mv_0c_v_slow.sdo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_8_1200mv_0c_v_slow.sdo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258435979 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_min_1200mv_0c_v_fast.sdo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_min_1200mv_0c_v_fast.sdo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258436421 ""}
|
||
|
|
{ "Info" "IWSC_DONE_HDL_GENERATION" "agi_fpga_v.sdo C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/ simulation " "Generated file agi_fpga_v.sdo in folder \"C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "EDA Netlist Writer" 0 -1 1718258436813 ""}
|
||
|
|
{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 1 Quartus Prime " "Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "4674 " "Peak virtual memory: 4674 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1718258438226 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Jun 13 14:00:38 2024 " "Processing ended: Thu Jun 13 14:00:38 2024" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1718258438226 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Elapsed time: 00:00:06" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1718258438226 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:05 " "Total CPU time (on all processors): 00:00:05" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1718258438226 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1718258438226 ""}
|
||
|
|
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 55 s " "Quartus Prime Full Compilation was successful. 0 errors, 55 warnings" { } { } 0 293000 "Quartus Prime %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "EDA Netlist Writer" 0 -1 1718258438871 ""}
|