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1462 lines
287 KiB
Plaintext
1462 lines
287 KiB
Plaintext
5 months ago
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Analysis & Synthesis report for agi_fpga
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Thu Jun 20 16:28:19 2024
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Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Analysis & Synthesis Summary
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3. Analysis & Synthesis Settings
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4. Parallel Compilation
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5. Analysis & Synthesis Source Files Read
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6. Analysis & Synthesis Resource Usage Summary
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7. Analysis & Synthesis Resource Utilization by Entity
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8. Analysis & Synthesis RAM Summary
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9. Analysis & Synthesis IP Cores Summary
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10. User-Specified and Inferred Latches
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11. Registers Removed During Synthesis
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12. General Register Statistics
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13. Inverted Register Statistics
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14. Multiplexer Restructuring Statistics (Restructuring Performed)
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15. Source assignments for sld_signaltap:auto_signaltap_0
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16. Parameter Settings for User Entity Instance: uart_rx:uart_rx_inst
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17. Parameter Settings for User Entity Instance: uart_tx:uart_tx_inst
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18. Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst
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19. Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst
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20. Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst
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21. Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst
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22. Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst
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23. Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0
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24. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1
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25. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2
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26. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2
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27. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0
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28. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0
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29. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0
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30. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0
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31. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1
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32. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1
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33. Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1
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34. Port Connectivity Checks: "uart_tx:uart_tx_inst"
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35. Signal Tap Logic Analyzer Settings
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36. Post-Synthesis Netlist Statistics for Top Partition
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37. Elapsed Time Per Partition
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38. Connections to In-System Debugging Instance "auto_signaltap_0"
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39. Analysis & Synthesis Messages
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40. Analysis & Synthesis Suppressed Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 2018 Intel Corporation. All rights reserved.
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Your use of Intel Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Intel Program License
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Subscription Agreement, the Intel Quartus Prime License Agreement,
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the Intel FPGA IP License Agreement, or other applicable license
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agreement, including, without limitation, that your use is for
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the sole purpose of programming logic devices manufactured by
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Intel and sold by Intel or its authorized distributors. Please
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refer to the applicable agreement for further details.
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+----------------------------------------------------------------------------------+
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; Analysis & Synthesis Summary ;
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+------------------------------------+---------------------------------------------+
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; Analysis & Synthesis Status ; Successful - Thu Jun 20 16:28:19 2024 ;
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; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ;
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; Revision Name ; agi_fpga ;
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; Top-level Entity Name ; stark_machine ;
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; Family ; Cyclone IV E ;
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; Total logic elements ; 2,783 ;
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; Total combinational functions ; 2,122 ;
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; Dedicated logic registers ; 1,320 ;
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; Total registers ; 1320 ;
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; Total pins ; 24 ;
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; Total virtual pins ; 0 ;
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; Total memory bits ; 102,400 ;
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; Embedded Multiplier 9-bit elements ; 0 ;
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; Total PLLs ; 0 ;
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+------------------------------------+---------------------------------------------+
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+------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Settings ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Option ; Setting ; Default Value ;
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+------------------------------------------------------------------+--------------------+--------------------+
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; Device ; EP4CE6F17C8 ; ;
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; Top-level entity name ; stark_machine ; agi_fpga ;
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; Family name ; Cyclone IV E ; Cyclone V ;
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; Use smart compilation ; Off ; Off ;
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; Enable parallel Assembler and Timing Analyzer during compilation ; On ; On ;
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; Enable compact report table ; Off ; Off ;
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; Restructure Multiplexers ; Auto ; Auto ;
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; Create Debugging Nodes for IP Cores ; Off ; Off ;
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; Preserve fewer node names ; On ; On ;
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; Intel FPGA IP Evaluation Mode ; Enable ; Enable ;
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; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
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; VHDL Version ; VHDL_1993 ; VHDL_1993 ;
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; State Machine Processing ; Auto ; Auto ;
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; Safe State Machine ; Off ; Off ;
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; Extract Verilog State Machines ; On ; On ;
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; Extract VHDL State Machines ; On ; On ;
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; Ignore Verilog initial constructs ; Off ; Off ;
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; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
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; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
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; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
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; Infer RAMs from Raw Logic ; On ; On ;
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; Parallel Synthesis ; On ; On ;
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; DSP Block Balancing ; Auto ; Auto ;
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; NOT Gate Push-Back ; On ; On ;
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; Power-Up Don't Care ; On ; On ;
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; Remove Redundant Logic Cells ; Off ; Off ;
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; Remove Duplicate Registers ; On ; On ;
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; Ignore CARRY Buffers ; Off ; Off ;
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; Ignore CASCADE Buffers ; Off ; Off ;
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; Ignore GLOBAL Buffers ; Off ; Off ;
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; Ignore ROW GLOBAL Buffers ; Off ; Off ;
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; Ignore LCELL Buffers ; Off ; Off ;
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; Ignore SOFT Buffers ; On ; On ;
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; Limit AHDL Integers to 32 Bits ; Off ; Off ;
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; Optimization Technique ; Balanced ; Balanced ;
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; Carry Chain Length ; 70 ; 70 ;
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; Auto Carry Chains ; On ; On ;
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; Auto Open-Drain Pins ; On ; On ;
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; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
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; Auto ROM Replacement ; On ; On ;
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; Auto RAM Replacement ; On ; On ;
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; Auto DSP Block Replacement ; On ; On ;
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; Auto Shift Register Replacement ; Auto ; Auto ;
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; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ;
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; Auto Clock Enable Replacement ; On ; On ;
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; Strict RAM Replacement ; Off ; Off ;
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; Allow Synchronous Control Signals ; On ; On ;
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; Force Use of Synchronous Clear Signals ; Off ; Off ;
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; Auto RAM Block Balancing ; On ; On ;
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; Auto RAM to Logic Cell Conversion ; Off ; Off ;
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; Auto Resource Sharing ; Off ; Off ;
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; Allow Any RAM Size For Recognition ; Off ; Off ;
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; Allow Any ROM Size For Recognition ; Off ; Off ;
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; Allow Any Shift Register Size For Recognition ; Off ; Off ;
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; Use LogicLock Constraints during Resource Balancing ; On ; On ;
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; Ignore translate_off and synthesis_off directives ; Off ; Off ;
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; Timing-Driven Synthesis ; On ; On ;
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; Report Parameter Settings ; On ; On ;
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; Report Source Assignments ; On ; On ;
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; Report Connectivity Checks ; On ; On ;
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; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
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; Synchronization Register Chain Length ; 2 ; 2 ;
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; Power Optimization During Synthesis ; Normal compilation ; Normal compilation ;
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; HDL message level ; Level2 ; Level2 ;
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; Suppress Register Optimization Related Messages ; Off ; Off ;
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; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ;
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; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
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; Clock MUX Protection ; On ; On ;
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; Auto Gated Clock Conversion ; Off ; Off ;
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; Block Design Naming ; Auto ; Auto ;
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; SDC constraint protection ; Off ; Off ;
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; Synthesis Effort ; Auto ; Auto ;
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; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
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; Pre-Mapping Resynthesis Optimization ; Off ; Off ;
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; Analysis & Synthesis Message Level ; Medium ; Medium ;
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; Disable Register Merging Across Hierarchies ; Auto ; Auto ;
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; Resource Aware Inference For Block RAM ; On ; On ;
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+------------------------------------------------------------------+--------------------+--------------------+
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+------------------------------------------+
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; Parallel Compilation ;
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+----------------------------+-------------+
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; Processors ; Number ;
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+----------------------------+-------------+
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; Number detected on machine ; 8 ;
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; Maximum allowed ; 4 ;
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; ; ;
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; Average used ; 1.00 ;
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; Maximum used ; 4 ;
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; ; ;
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; Usage by Processor ; % Time Used ;
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; Processor 1 ; 100.0% ;
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; Processor 2 ; 0.0% ;
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; Processor 3 ; 0.0% ;
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; Processor 4 ; 0.0% ;
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+----------------------------+-------------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Analysis & Synthesis Source Files Read ;
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+--------------------------------------------------------------------+-----------------+----------------------------------------------+---------------------------------------------------------------------------------------------------------------------+-------------+
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; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ;
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+--------------------------------------------------------------------+-----------------+----------------------------------------------+---------------------------------------------------------------------------------------------------------------------+-------------+
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; ../rtl/uart/uart_tx.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v ; ;
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; ../rtl/uart/uart_rx.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v ; ;
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; ../rtl/uart/param.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/param.v ; ;
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; ../rtl/ws2812/ws2812_ctrl.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v ; ;
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; ../rtl/ws2812/ws2812_circuit.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v ; ;
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; ../rtl/ws2812/data_cfg.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v ; ;
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; ../rtl/digit_led/timer_decoder.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v ; ;
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; ../rtl/digit_led/timer.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v ; ;
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; ../rtl/digit_led/clock_circuit.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v ; ;
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; ../rtl/beep/pwm_beep.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v ; ;
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; ../rtl/beep/freq_select.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v ; ;
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; ../rtl/beep/beep_circuit.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v ; ;
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; ../rtl/led/led_circuit.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v ; ;
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; ../rtl/stark_machine.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v ; ;
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; ../rtl/instr_decode.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/instr_decode.v ; ;
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; ../rtl/circuit_arb.v ; yes ; User Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v ; ;
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; sld_signaltap.vhd ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_signaltap.vhd ; ;
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; sld_signaltap_impl.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_signaltap_impl.vhd ; ;
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; sld_ela_control.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_ela_control.vhd ; ;
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; lpm_shiftreg.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_shiftreg.tdf ; ;
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; lpm_constant.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_constant.inc ; ;
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; dffeea.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/dffeea.inc ; ;
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; aglobal181.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/aglobal181.inc ; ;
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; sld_mbpmg.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_mbpmg.vhd ; ;
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; sld_ela_trigger_flow_mgr.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_ela_trigger_flow_mgr.vhd ; ;
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; sld_buffer_manager.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_buffer_manager.vhd ; ;
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; altsyncram.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf ; ;
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; stratix_ram_block.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/stratix_ram_block.inc ; ;
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; lpm_mux.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_mux.inc ; ;
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; lpm_decode.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_decode.inc ; ;
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; a_rdenreg.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/a_rdenreg.inc ; ;
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; altrom.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altrom.inc ; ;
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; altram.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altram.inc ; ;
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; altdpram.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altdpram.inc ; ;
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; db/altsyncram_sa24.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/altsyncram_sa24.tdf ; ;
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; altdpram.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altdpram.tdf ; ;
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; memmodes.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/others/maxplus2/memmodes.inc ; ;
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; a_hdffe.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/a_hdffe.inc ; ;
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; alt_le_rden_reg.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/alt_le_rden_reg.inc ; ;
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; altsyncram.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altsyncram.inc ; ;
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; lpm_mux.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_mux.tdf ; ;
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; muxlut.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/muxlut.inc ; ;
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; bypassff.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/bypassff.inc ; ;
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; altshift.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/altshift.inc ; ;
|
||
|
|
; db/mux_rsc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/mux_rsc.tdf ; ;
|
||
|
|
; lpm_decode.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_decode.tdf ; ;
|
||
|
|
; declut.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/declut.inc ; ;
|
||
|
|
; lpm_compare.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_compare.inc ; ;
|
||
|
|
; db/decode_dvf.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/decode_dvf.tdf ; ;
|
||
|
|
; lpm_counter.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_counter.tdf ; ;
|
||
|
|
; lpm_add_sub.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_add_sub.inc ; ;
|
||
|
|
; cmpconst.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/cmpconst.inc ; ;
|
||
|
|
; lpm_counter.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_counter.inc ; ;
|
||
|
|
; alt_counter_stratix.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/alt_counter_stratix.inc ; ;
|
||
|
|
; db/cntr_fgi.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_fgi.tdf ; ;
|
||
|
|
; db/cmpr_sgc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_sgc.tdf ; ;
|
||
|
|
; db/cntr_g9j.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_g9j.tdf ; ;
|
||
|
|
; db/cntr_egi.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_egi.tdf ; ;
|
||
|
|
; db/cmpr_rgc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_rgc.tdf ; ;
|
||
|
|
; db/cntr_23j.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_23j.tdf ; ;
|
||
|
|
; db/cmpr_ngc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_ngc.tdf ; ;
|
||
|
|
; sld_rom_sr.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_rom_sr.vhd ; ;
|
||
|
|
; sld_jtag_endpoint_adapter.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter.vhd ; ;
|
||
|
|
; sld_jtag_endpoint_adapter_impl.sv ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_jtag_endpoint_adapter_impl.sv ; ;
|
||
|
|
; sld_hub.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_hub.vhd ; altera_sld ;
|
||
|
|
; db/ip/sldbacf2b6c/alt_sld_fab.v ; yes ; Encrypted Auto-Found Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/alt_sld_fab.v ; alt_sld_fab ;
|
||
|
|
; db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v ; yes ; Encrypted Auto-Found Verilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v ; alt_sld_fab ;
|
||
|
|
; db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv ; yes ; Auto-Found SystemVerilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv ; alt_sld_fab ;
|
||
|
|
; db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv ; yes ; Encrypted Auto-Found SystemVerilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv ; alt_sld_fab ;
|
||
|
|
; db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; yes ; Encrypted Auto-Found VHDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd ; alt_sld_fab ;
|
||
|
|
; db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv ; yes ; Encrypted Auto-Found SystemVerilog HDL File ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv ; alt_sld_fab ;
|
||
|
|
; sld_jtag_hub.vhd ; yes ; Encrypted Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sld_jtag_hub.vhd ; ;
|
||
|
|
; lpm_divide.tdf ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/lpm_divide.tdf ; ;
|
||
|
|
; abs_divider.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/abs_divider.inc ; ;
|
||
|
|
; sign_div_unsign.inc ; yes ; Megafunction ; d:/intelfpga_lite/18.1/quartus/libraries/megafunctions/sign_div_unsign.inc ; ;
|
||
|
|
; db/lpm_divide_8bm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_8bm.tdf ; ;
|
||
|
|
; db/sign_div_unsign_tlh.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_tlh.tdf ; ;
|
||
|
|
; db/alt_u_div_e7f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_e7f.tdf ; ;
|
||
|
|
; db/add_sub_7pc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_7pc.tdf ; ;
|
||
|
|
; db/add_sub_8pc.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_8pc.tdf ; ;
|
||
|
|
; db/lpm_divide_k9m.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_k9m.tdf ; ;
|
||
|
|
; db/sign_div_unsign_9kh.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_9kh.tdf ; ;
|
||
|
|
; db/alt_u_div_64f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf ; ;
|
||
|
|
; db/lpm_divide_hhm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_hhm.tdf ; ;
|
||
|
|
; db/lpm_divide_ikm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ikm.tdf ; ;
|
||
|
|
; db/sign_div_unsign_anh.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_anh.tdf ; ;
|
||
|
|
; db/alt_u_div_8af.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_8af.tdf ; ;
|
||
|
|
; db/lpm_divide_ghm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ghm.tdf ; ;
|
||
|
|
; db/sign_div_unsign_8kh.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_8kh.tdf ; ;
|
||
|
|
; db/alt_u_div_44f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf ; ;
|
||
|
|
; db/lpm_divide_j9m.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_j9m.tdf ; ;
|
||
|
|
; db/lpm_divide_lcm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_lcm.tdf ; ;
|
||
|
|
; db/lpm_divide_0jm.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_0jm.tdf ; ;
|
||
|
|
; db/sign_div_unsign_olh.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_olh.tdf ; ;
|
||
|
|
; db/alt_u_div_47f.tdf ; yes ; Auto-Generated Megafunction ; C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_47f.tdf ; ;
|
||
|
|
; ../rtl/led_circuit.v ; yes ; User Verilog HDL File ; ../rtl/led_circuit.v ; ;
|
||
|
|
; /users/stark-lin/desktop/agi_fpga/hardware/rtl/param.v ; yes ; Auto-Found Verilog HDL File ; /users/stark-lin/desktop/agi_fpga/hardware/rtl/param.v ; ;
|
||
|
|
+--------------------------------------------------------------------+-----------------+----------------------------------------------+---------------------------------------------------------------------------------------------------------------------+-------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------+
|
||
|
|
; Analysis & Synthesis Resource Usage Summary ;
|
||
|
|
+---------------------------------------------+---------------+
|
||
|
|
; Resource ; Usage ;
|
||
|
|
+---------------------------------------------+---------------+
|
||
|
|
; Estimated Total logic elements ; 2,783 ;
|
||
|
|
; ; ;
|
||
|
|
; Total combinational functions ; 2122 ;
|
||
|
|
; Logic element usage by number of LUT inputs ; ;
|
||
|
|
; -- 4 input functions ; 689 ;
|
||
|
|
; -- 3 input functions ; 536 ;
|
||
|
|
; -- <=2 input functions ; 897 ;
|
||
|
|
; ; ;
|
||
|
|
; Logic elements by mode ; ;
|
||
|
|
; -- normal mode ; 1567 ;
|
||
|
|
; -- arithmetic mode ; 555 ;
|
||
|
|
; ; ;
|
||
|
|
; Total registers ; 1320 ;
|
||
|
|
; -- Dedicated logic registers ; 1320 ;
|
||
|
|
; -- I/O registers ; 0 ;
|
||
|
|
; ; ;
|
||
|
|
; I/O pins ; 24 ;
|
||
|
|
; Total memory bits ; 102400 ;
|
||
|
|
; ; ;
|
||
|
|
; Embedded Multiplier 9-bit elements ; 0 ;
|
||
|
|
; ; ;
|
||
|
|
; Maximum fan-out node ; sys_clk~input ;
|
||
|
|
; Maximum fan-out ; 873 ;
|
||
|
|
; Total fan-out ; 11713 ;
|
||
|
|
; Average fan-out ; 3.30 ;
|
||
|
|
+---------------------------------------------+---------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Analysis & Synthesis Resource Utilization by Entity ;
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
|
||
|
|
; Compilation Hierarchy Node ; Combinational ALUTs ; Dedicated Logic Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Entity Name ; Library Name ;
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
|
||
|
|
; |stark_machine ; 2122 (26) ; 1320 (26) ; 102400 ; 0 ; 0 ; 0 ; 24 ; 0 ; |stark_machine ; stark_machine ; work ;
|
||
|
|
; |circuit_arb:circuit_arb_inst| ; 1369 (3) ; 198 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst ; circuit_arb ; work ;
|
||
|
|
; |beep_circuit:beep_circuit_inst| ; 139 (0) ; 48 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst ; beep_circuit ; work ;
|
||
|
|
; |freq_select:freq_select_inst| ; 139 (139) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst ; freq_select ; work ;
|
||
|
|
; |pwm_beep:pwm_beep_inst| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|pwm_beep:pwm_beep_inst ; pwm_beep ; work ;
|
||
|
|
; |clock_circuit:clock_circuit_inst| ; 1044 (0) ; 63 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst ; clock_circuit ; work ;
|
||
|
|
; |timer:timer_inst| ; 798 (63) ; 46 (46) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst ; timer ; work ;
|
||
|
|
; |lpm_divide:Div0| ; 176 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0 ; lpm_divide ; work ;
|
||
|
|
; |lpm_divide_ikm:auto_generated| ; 176 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated ; lpm_divide_ikm ; work ;
|
||
|
|
; |sign_div_unsign_anh:divider| ; 176 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated|sign_div_unsign_anh:divider ; sign_div_unsign_anh ; work ;
|
||
|
|
; |alt_u_div_8af:divider| ; 176 (176) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0|lpm_divide_ikm:auto_generated|sign_div_unsign_anh:divider|alt_u_div_8af:divider ; alt_u_div_8af ; work ;
|
||
|
|
; |lpm_divide:Div1| ; 122 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1 ; lpm_divide ; work ;
|
||
|
|
; |lpm_divide_0jm:auto_generated| ; 122 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated ; lpm_divide_0jm ; work ;
|
||
|
|
; |sign_div_unsign_olh:divider| ; 122 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated|sign_div_unsign_olh:divider ; sign_div_unsign_olh ; work ;
|
||
|
|
; |alt_u_div_47f:divider| ; 122 (122) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1|lpm_divide_0jm:auto_generated|sign_div_unsign_olh:divider|alt_u_div_47f:divider ; alt_u_div_47f ; work ;
|
||
|
|
; |lpm_divide:Mod0| ; 211 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0 ; lpm_divide ; work ;
|
||
|
|
; |lpm_divide_lcm:auto_generated| ; 211 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated ; lpm_divide_lcm ; work ;
|
||
|
|
; |sign_div_unsign_anh:divider| ; 211 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated|sign_div_unsign_anh:divider ; sign_div_unsign_anh ; work ;
|
||
|
|
; |alt_u_div_8af:divider| ; 211 (211) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0|lpm_divide_lcm:auto_generated|sign_div_unsign_anh:divider|alt_u_div_8af:divider ; alt_u_div_8af ; work ;
|
||
|
|
; |lpm_divide:Mod1| ; 226 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1 ; lpm_divide ; work ;
|
||
|
|
; |lpm_divide_8bm:auto_generated| ; 226 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated ; lpm_divide_8bm ; work ;
|
||
|
|
; |sign_div_unsign_tlh:divider| ; 226 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated|sign_div_unsign_tlh:divider ; sign_div_unsign_tlh ; work ;
|
||
|
|
; |alt_u_div_e7f:divider| ; 226 (226) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1|lpm_divide_8bm:auto_generated|sign_div_unsign_tlh:divider|alt_u_div_e7f:divider ; alt_u_div_e7f ; work ;
|
||
|
|
; |timer_decoder:timer_decoder_inst| ; 246 (77) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst ; timer_decoder ; work ;
|
||
|
|
; |lpm_divide:Div0| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0 ; lpm_divide ; work ;
|
||
|
|
; |lpm_divide_ghm:auto_generated| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated ; lpm_divide_ghm ; work ;
|
||
|
|
; |sign_div_unsign_8kh:divider| ; 18 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated|sign_div_unsign_8kh:divider ; sign_div_unsign_8kh ; work ;
|
||
|
|
; |alt_u_div_44f:divider| ; 18 (18) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider ; alt_u_div_44f ; work ;
|
||
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; |lpm_divide:Div1| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1 ; lpm_divide ; work ;
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; |lpm_divide_hhm:auto_generated| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated ; lpm_divide_hhm ; work ;
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; |sign_div_unsign_9kh:divider| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Div2| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2 ; lpm_divide ; work ;
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; |lpm_divide_hhm:auto_generated| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated ; lpm_divide_hhm ; work ;
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; |sign_div_unsign_9kh:divider| ; 32 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 32 (32) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Mod0| ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0 ; lpm_divide ; work ;
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; |lpm_divide_j9m:auto_generated| ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated ; lpm_divide_j9m ; work ;
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; |sign_div_unsign_8kh:divider| ; 21 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider ; sign_div_unsign_8kh ; work ;
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; |alt_u_div_44f:divider| ; 21 (21) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider ; alt_u_div_44f ; work ;
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; |lpm_divide:Mod1| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1 ; lpm_divide ; work ;
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; |lpm_divide_k9m:auto_generated| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated ; lpm_divide_k9m ; work ;
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; |sign_div_unsign_9kh:divider| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |lpm_divide:Mod2| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2 ; lpm_divide ; work ;
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; |lpm_divide_k9m:auto_generated| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated ; lpm_divide_k9m ; work ;
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; |sign_div_unsign_9kh:divider| ; 33 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider ; sign_div_unsign_9kh ; work ;
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; |alt_u_div_64f:divider| ; 33 (33) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider ; alt_u_div_64f ; work ;
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; |led_circuit:led_circuit_inst| ; 67 (67) ; 33 (33) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst ; led_circuit ; work ;
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; |ws2812_circuit:ws2812_circuit_inst| ; 116 (0) ; 54 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst ; ws2812_circuit ; work ;
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; |data_cfg:data_cfg_inst| ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|data_cfg:data_cfg_inst ; data_cfg ; work ;
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; |ws2812_ctrl:ws2812_ctrl_inst| ; 93 (93) ; 54 (54) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst ; ws2812_ctrl ; work ;
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; |sld_hub:auto_hub| ; 128 (1) ; 91 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub ; sld_hub ; altera_sld ;
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; |alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric| ; 127 (0) ; 91 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric ; alt_sld_fab_with_jtag_input ; altera_sld ;
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; |alt_sld_fab:instrumentation_fabric| ; 127 (0) ; 91 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab:alt_sld_fab| ; 127 (1) ; 91 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; alt_sld_fab_alt_sld_fab ; alt_sld_fab ;
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; |alt_sld_fab_alt_sld_fab_sldfabric:sldfabric| ; 126 (0) ; 86 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; alt_sld_fab_alt_sld_fab_sldfabric ; alt_sld_fab ;
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; |sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub| ; 126 (87) ; 86 (58) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub ; sld_jtag_hub ; work ;
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; |sld_rom_sr:hub_info_reg| ; 21 (21) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_rom_sr:hub_info_reg ; sld_rom_sr ; work ;
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; |sld_shadow_jsm:shadow_jsm| ; 18 (18) ; 19 (19) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|sld_shadow_jsm:shadow_jsm ; sld_shadow_jsm ; altera_sld ;
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; |sld_signaltap:auto_signaltap_0| ; 514 (2) ; 950 (100) ; 102400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0 ; sld_signaltap ; work ;
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; |sld_signaltap_impl:sld_signaltap_body| ; 512 (0) ; 850 (0) ; 102400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body ; sld_signaltap_impl ; work ;
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; |sld_signaltap_implb:sld_signaltap_body| ; 512 (88) ; 850 (282) ; 102400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body ; sld_signaltap_implb ; work ;
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; |altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem| ; 25 (0) ; 70 (70) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem ; altdpram ; work ;
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; |lpm_decode:wdecoder| ; 2 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder ; lpm_decode ; work ;
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; |decode_dvf:auto_generated| ; 2 (2) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_decode:wdecoder|decode_dvf:auto_generated ; decode_dvf ; work ;
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; |lpm_mux:mux| ; 23 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux ; lpm_mux ; work ;
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; |mux_rsc:auto_generated| ; 23 (23) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altdpram:\stp_non_zero_ram_gen:attribute_mem_gen:attribute_mem|lpm_mux:mux|mux_rsc:auto_generated ; mux_rsc ; work ;
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; |altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram| ; 0 (0) ; 0 (0) ; 102400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram ; altsyncram ; work ;
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; |altsyncram_sa24:auto_generated| ; 0 (0) ; 0 (0) ; 102400 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_sa24:auto_generated ; altsyncram_sa24 ; work ;
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; |lpm_shiftreg:segment_offset_config_deserialize| ; 0 (0) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:segment_offset_config_deserialize ; lpm_shiftreg ; work ;
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; |lpm_shiftreg:status_register| ; 17 (17) ; 17 (17) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|lpm_shiftreg:status_register ; lpm_shiftreg ; work ;
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; |serial_crc_16:\tdo_crc_gen:tdo_crc_calc| ; 14 (14) ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|serial_crc_16:\tdo_crc_gen:tdo_crc_calc ; serial_crc_16 ; work ;
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; |sld_buffer_manager:sld_buffer_manager_inst| ; 85 (85) ; 64 (64) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst ; sld_buffer_manager ; work ;
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; |sld_ela_control:ela_control| ; 118 (1) ; 266 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control ; sld_ela_control ; work ;
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; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 4 (4) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|lpm_shiftreg:trigger_config_deserialize ; lpm_shiftreg ; work ;
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; |sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm| ; 100 (0) ; 250 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm ; sld_ela_basic_multi_level_trigger ; work ;
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; |lpm_shiftreg:trigger_condition_deserialize| ; 0 (0) ; 150 (150) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|lpm_shiftreg:trigger_condition_deserialize ; lpm_shiftreg ; work ;
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; |sld_mbpmg:\trigger_modules_gen:0:trigger_match| ; 100 (0) ; 100 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match ; sld_mbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:0:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:10:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:11:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:12:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:13:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:14:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:15:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:16:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:17:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:18:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:19:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:1:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:20:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:21:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:22:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:23:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:24:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:25:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:26:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:27:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:28:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:29:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:2:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:30:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:31:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:32:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:33:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:34:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:35:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:36:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:37:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:38:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:39:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:3:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:40:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:41:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:42:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:43:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:44:sm1 ; sld_sbpmg ; work ;
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; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:45:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:46:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:47:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:48:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:49:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:4:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:5:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:6:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:7:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:8:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1| ; 2 (2) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_basic_multi_level_trigger:\basic_multi_level_mbpm_trigger_gen:multi_level_mbpm|sld_mbpmg:\trigger_modules_gen:0:trigger_match|sld_sbpmg:\gen_sbpmg_pipeline_less_than_two:sm0:9:sm1 ; sld_sbpmg ; work ;
|
||
|
|
; |sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity| ; 17 (17) ; 11 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity ; sld_ela_trigger_flow_mgr ; work ;
|
||
|
|
; |lpm_shiftreg:trigger_config_deserialize| ; 0 (0) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_ela_control:ela_control|sld_ela_trigger_flow_mgr:\builtin:ela_trigger_flow_mgr_entity|lpm_shiftreg:trigger_config_deserialize ; lpm_shiftreg ; work ;
|
||
|
|
; |sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst| ; 135 (10) ; 119 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst ; sld_offload_buffer_mgr ; work ;
|
||
|
|
; |lpm_counter:\adv_point_3_and_more:advance_pointer_counter| ; 8 (0) ; 6 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter ; lpm_counter ; work ;
|
||
|
|
; |cntr_fgi:auto_generated| ; 8 (8) ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:\adv_point_3_and_more:advance_pointer_counter|cntr_fgi:auto_generated ; cntr_fgi ; work ;
|
||
|
|
; |lpm_counter:read_pointer_counter| ; 11 (0) ; 11 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter ; lpm_counter ; work ;
|
||
|
|
; |cntr_g9j:auto_generated| ; 11 (11) ; 11 (11) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:read_pointer_counter|cntr_g9j:auto_generated ; cntr_g9j ; work ;
|
||
|
|
; |lpm_counter:status_advance_pointer_counter| ; 7 (0) ; 5 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter ; lpm_counter ; work ;
|
||
|
|
; |cntr_egi:auto_generated| ; 7 (7) ; 5 (5) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_advance_pointer_counter|cntr_egi:auto_generated ; cntr_egi ; work ;
|
||
|
|
; |lpm_counter:status_read_pointer_counter| ; 3 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter ; lpm_counter ; work ;
|
||
|
|
; |cntr_23j:auto_generated| ; 3 (3) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_counter:status_read_pointer_counter|cntr_23j:auto_generated ; cntr_23j ; work ;
|
||
|
|
; |lpm_shiftreg:info_data_shift_out| ; 23 (23) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:info_data_shift_out ; lpm_shiftreg ; work ;
|
||
|
|
; |lpm_shiftreg:ram_data_shift_out| ; 50 (50) ; 50 (50) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:ram_data_shift_out ; lpm_shiftreg ; work ;
|
||
|
|
; |lpm_shiftreg:status_data_shift_out| ; 23 (23) ; 23 (23) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_offload_buffer_mgr:\stp_non_zero_depth_offload_gen:stp_offload_buff_mgr_inst|lpm_shiftreg:status_data_shift_out ; lpm_shiftreg ; work ;
|
||
|
|
; |sld_rom_sr:crc_rom_sr| ; 30 (30) ; 8 (8) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_rom_sr:crc_rom_sr ; sld_rom_sr ; work ;
|
||
|
|
; |uart_rx:uart_rx_inst| ; 49 (49) ; 28 (28) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|uart_rx:uart_rx_inst ; uart_rx ; work ;
|
||
|
|
; |uart_tx:uart_tx_inst| ; 36 (36) ; 27 (27) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |stark_machine|uart_tx:uart_tx_inst ; uart_tx ; work ;
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------+---------------------+---------------------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------+--------------+
|
||
|
|
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Analysis & Synthesis RAM Summary ;
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
|
||
|
|
; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|altsyncram:\stp_non_zero_ram_gen:stp_buffer_ram|altsyncram_sa24:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 50 ; 2048 ; 50 ; 102400 ; None ;
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------+------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Analysis & Synthesis IP Cores Summary ;
|
||
|
|
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
|
||
|
|
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance ; IP Include File ;
|
||
|
|
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
|
||
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric ; ;
|
||
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab ; ;
|
||
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_presplit:presplit ; ;
|
||
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric ; ;
|
||
|
|
; Altera ; Signal Tap ; N/A ; N/A ; Licensed ; |stark_machine|sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_splitter:splitter ; ;
|
||
|
|
+--------+--------------+---------+--------------+--------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; User-Specified and Inferred Latches ;
|
||
|
|
+--------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------+
|
||
|
|
; Latch Name ; Latch Enable Signal ; Free of Timing Hazards ;
|
||
|
|
+--------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------+
|
||
|
|
; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[1] ; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|WideNor0 ; yes ;
|
||
|
|
; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[5] ; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|WideNor0 ; yes ;
|
||
|
|
; Number of user-specified and inferred latches = 2 ; ; ;
|
||
|
|
+--------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------+------------------------+
|
||
|
|
Note: All latches listed above may not be present at the end of synthesis due to various synthesis optimizations.
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------+
|
||
|
|
; Registers Removed During Synthesis ;
|
||
|
|
+---------------------------------------+----------------------------------------+
|
||
|
|
; Register name ; Reason for Removal ;
|
||
|
|
+---------------------------------------+----------------------------------------+
|
||
|
|
; uart_tx:uart_tx_inst|data_reg[0] ; Stuck at GND due to stuck port data_in ;
|
||
|
|
; Total Number of Removed Registers = 1 ; ;
|
||
|
|
+---------------------------------------+----------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------+
|
||
|
|
; General Register Statistics ;
|
||
|
|
+----------------------------------------------+-------+
|
||
|
|
; Statistic ; Value ;
|
||
|
|
+----------------------------------------------+-------+
|
||
|
|
; Total registers ; 1320 ;
|
||
|
|
; Number of registers using Synchronous Clear ; 199 ;
|
||
|
|
; Number of registers using Synchronous Load ; 69 ;
|
||
|
|
; Number of registers using Asynchronous Clear ; 628 ;
|
||
|
|
; Number of registers using Asynchronous Load ; 0 ;
|
||
|
|
; Number of registers using Clock Enable ; 723 ;
|
||
|
|
; Number of registers using Preset ; 0 ;
|
||
|
|
+----------------------------------------------+-------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Inverted Register Statistics ;
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
||
|
|
; Inverted Register ; Fan out ;
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
||
|
|
; uart_tx:uart_tx_inst|tx_dout ; 1 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|pwm_beep:pwm_beep_inst|beep ; 1 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[1] ; 10 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[0] ; 12 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[3] ; 6 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[2] ; 7 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[5] ; 5 ;
|
||
|
|
; circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[4] ; 5 ;
|
||
|
|
; uart_rx:uart_rx_inst|din_reg0 ; 10 ;
|
||
|
|
; uart_rx:uart_rx_inst|din_reg1 ; 1 ;
|
||
|
|
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[2] ; 2 ;
|
||
|
|
; sld_hub:auto_hub|alt_sld_fab_with_jtag_input:\instrumentation_fabric_with_node_gen:fabric_gen_new_way:with_jtag_input_gen:instrumentation_fabric|alt_sld_fab:instrumentation_fabric|alt_sld_fab_alt_sld_fab:alt_sld_fab|alt_sld_fab_alt_sld_fab_sldfabric:sldfabric|sld_jtag_hub:\jtag_hub_gen:real_sld_jtag_hub|jtag_ir_reg[1] ; 3 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[1] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[2] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[3] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[4] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[5] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[6] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[7] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[8] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[9] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[10] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[11] ; 1 ;
|
||
|
|
; sld_signaltap:auto_signaltap_0|sld_signaltap_impl:sld_signaltap_body|sld_signaltap_implb:sld_signaltap_body|sld_buffer_manager:sld_buffer_manager_inst|modified_post_count[0] ; 1 ;
|
||
|
|
; Total number of inverted registers = 24 ; ;
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------+
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Multiplexer Restructuring Statistics (Restructuring Performed) ;
|
||
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
|
||
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |stark_machine|byte_num[0] ;
|
||
|
|
; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst|led[0] ;
|
||
|
|
; 4:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|frame[1] ;
|
||
|
|
; 4:1 ; 16 bits ; 32 LEs ; 16 LEs ; 16 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_freq[6] ;
|
||
|
|
; 4:1 ; 24 bits ; 48 LEs ; 24 LEs ; 24 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_300[23] ;
|
||
|
|
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|cnt_note[0] ;
|
||
|
|
; 4:1 ; 26 bits ; 52 LEs ; 26 LEs ; 26 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_rst[9] ;
|
||
|
|
; 4:1 ; 28 bits ; 56 LEs ; 28 LEs ; 28 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_s[12] ;
|
||
|
|
; 4:1 ; 17 bits ; 34 LEs ; 17 LEs ; 17 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|cnt_day[4] ;
|
||
|
|
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_0[5] ;
|
||
|
|
; 4:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|cnt_1[0] ;
|
||
|
|
; 4:1 ; 5 bits ; 10 LEs ; 5 LEs ; 5 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|bit_num[2] ;
|
||
|
|
; 4:1 ; 7 bits ; 14 LEs ; 7 LEs ; 7 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst|led_num[2] ;
|
||
|
|
; 4:1 ; 10 bits ; 20 LEs ; 10 LEs ; 10 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|cnt_fps[0] ;
|
||
|
|
; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|sel_led[0] ;
|
||
|
|
; 64:1 ; 4 bits ; 168 LEs ; 28 LEs ; 140 LEs ; No ; |stark_machine|circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Selector3 ;
|
||
|
|
+--------------------+-----------+---------------+----------------------+------------------------+------------+--------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------+
|
||
|
|
; Source assignments for sld_signaltap:auto_signaltap_0 ;
|
||
|
|
+-----------------+-------+------+----------------------+
|
||
|
|
; Assignment ; Value ; From ; To ;
|
||
|
|
+-----------------+-------+------+----------------------+
|
||
|
|
; MESSAGE_DISABLE ; 13410 ; - ; - ;
|
||
|
|
+-----------------+-------+------+----------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: uart_rx:uart_rx_inst ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
; BAUD ; 434 ; Signed Integer ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: uart_tx:uart_tx_inst ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
; BAUD ; 434 ; Signed Integer ;
|
||
|
|
+----------------+-------+------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+--------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst ;
|
||
|
|
+----------------+------------------------------+--------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+------------------------------+--------------------------------------------------------+
|
||
|
|
; MAX ; 0010111110101111000010000000 ; Unsigned Binary ;
|
||
|
|
+----------------+------------------------------+--------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst ;
|
||
|
|
+----------------+--------------------------+-------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+--------------------------+-------------------------------------------------------------------------------------------+
|
||
|
|
; MAX ; 111001001110000111000000 ; Unsigned Binary ;
|
||
|
|
; TWO_TIGER ; 100010 ; Unsigned Binary ;
|
||
|
|
; SKY_CITY ; 000000 ; Unsigned Binary ;
|
||
|
|
; DO ; 1011101010000110 ; Unsigned Binary ;
|
||
|
|
; RE ; 1010011000110110 ; Unsigned Binary ;
|
||
|
|
; MI ; 1001010000001100 ; Unsigned Binary ;
|
||
|
|
; FA ; 1001001010101110 ; Unsigned Binary ;
|
||
|
|
; SO ; 0111110001101010 ; Unsigned Binary ;
|
||
|
|
; LA ; 0110111011110000 ; Unsigned Binary ;
|
||
|
|
; XI ; 0110001100111000 ; Unsigned Binary ;
|
||
|
|
+----------------+--------------------------+-------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst ;
|
||
|
|
+----------------+------------------------------+-----------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+------------------------------+-----------------------------------------------------------------------------+
|
||
|
|
; MAX ; 0010111110101111000010000000 ; Unsigned Binary ;
|
||
|
|
; DAY ; 10101000110000000 ; Unsigned Binary ;
|
||
|
|
+----------------+------------------------------+-----------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+---------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst ;
|
||
|
|
+----------------+------------+---------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+------------+---------------------------------------------------------------------------------------------------------------+
|
||
|
|
; FPS ; 1111101000 ; Unsigned Binary ;
|
||
|
|
+----------------+------------+---------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for User Entity Instance: circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst ;
|
||
|
|
+----------------+----------------------------+---------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+----------------+----------------------------+---------------------------------------------------------------------------------------------+
|
||
|
|
; T0H ; 1101 ; Unsigned Binary ;
|
||
|
|
; T0L ; 11110 ; Unsigned Binary ;
|
||
|
|
; T1H ; 11110 ; Unsigned Binary ;
|
||
|
|
; T1L ; 11110 ; Unsigned Binary ;
|
||
|
|
; RST ; 00010011000100101101000000 ; Unsigned Binary ;
|
||
|
|
; BIT ; 11000 ; Unsigned Binary ;
|
||
|
|
; LED ; 1000000 ; Unsigned Binary ;
|
||
|
|
+----------------+----------------------------+---------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: sld_signaltap:auto_signaltap_0 ;
|
||
|
|
+-------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+-------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
|
||
|
|
; lpm_type ; sld_signaltap ; String ;
|
||
|
|
; sld_node_info ; 805334528 ; Untyped ;
|
||
|
|
; SLD_SECTION_ID ; hdl_signaltap_0 ; String ;
|
||
|
|
; SLD_IP_VERSION ; 6 ; Signed Integer ;
|
||
|
|
; SLD_IP_MINOR_VERSION ; 0 ; Signed Integer ;
|
||
|
|
; SLD_COMMON_IP_VERSION ; 0 ; Signed Integer ;
|
||
|
|
; sld_data_bits ; 50 ; Untyped ;
|
||
|
|
; sld_trigger_bits ; 50 ; Untyped ;
|
||
|
|
; SLD_NODE_CRC_BITS ; 32 ; Signed Integer ;
|
||
|
|
; SLD_NODE_CRC_HIWORD ; 41394 ; Signed Integer ;
|
||
|
|
; SLD_NODE_CRC_LOWORD ; 50132 ; Signed Integer ;
|
||
|
|
; sld_incremental_routing ; 1 ; Untyped ;
|
||
|
|
; sld_sample_depth ; 2048 ; Untyped ;
|
||
|
|
; sld_segment_size ; 2048 ; Untyped ;
|
||
|
|
; sld_ram_block_type ; AUTO ; Untyped ;
|
||
|
|
; sld_state_bits ; 11 ; Untyped ;
|
||
|
|
; sld_buffer_full_stop ; 1 ; Untyped ;
|
||
|
|
; SLD_MEM_ADDRESS_BITS ; 7 ; Signed Integer ;
|
||
|
|
; SLD_DATA_BIT_CNTR_BITS ; 4 ; Signed Integer ;
|
||
|
|
; sld_trigger_level ; 1 ; Untyped ;
|
||
|
|
; sld_trigger_in_enabled ; 0 ; Untyped ;
|
||
|
|
; SLD_HPS_TRIGGER_IN_ENABLED ; 0 ; Signed Integer ;
|
||
|
|
; SLD_HPS_TRIGGER_OUT_ENABLED ; 0 ; Signed Integer ;
|
||
|
|
; SLD_HPS_EVENT_ENABLED ; 0 ; Signed Integer ;
|
||
|
|
; SLD_HPS_EVENT_ID ; 0 ; Signed Integer ;
|
||
|
|
; sld_advanced_trigger_entity ; basic,1, ; Untyped ;
|
||
|
|
; sld_trigger_level_pipeline ; 1 ; Untyped ;
|
||
|
|
; sld_trigger_pipeline ; 0 ; Untyped ;
|
||
|
|
; sld_ram_pipeline ; 0 ; Untyped ;
|
||
|
|
; sld_counter_pipeline ; 0 ; Untyped ;
|
||
|
|
; sld_enable_advanced_trigger ; 0 ; Untyped ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_1 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_2 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_3 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_4 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_5 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_6 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_7 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_8 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_9 ; NONE ; String ;
|
||
|
|
; SLD_ADVANCED_TRIGGER_10 ; NONE ; String ;
|
||
|
|
; sld_inversion_mask_length ; 175 ; Untyped ;
|
||
|
|
; sld_inversion_mask ; 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; Untyped ;
|
||
|
|
; sld_power_up_trigger ; 0 ; Untyped ;
|
||
|
|
; SLD_STATE_FLOW_MGR_ENTITY ; state_flow_mgr_entity.vhd ; String ;
|
||
|
|
; sld_state_flow_use_generated ; 0 ; Untyped ;
|
||
|
|
; sld_current_resource_width ; 1 ; Untyped ;
|
||
|
|
; sld_attribute_mem_mode ; OFF ; Untyped ;
|
||
|
|
; sld_storage_qualifier_bits ; 50 ; Untyped ;
|
||
|
|
; SLD_STORAGE_QUALIFIER_GAP_RECORD ; 0 ; Signed Integer ;
|
||
|
|
; SLD_STORAGE_QUALIFIER_MODE ; OFF ; String ;
|
||
|
|
; SLD_STORAGE_QUALIFIER_ENABLE_ADVANCED_CONDITION ; 0 ; Signed Integer ;
|
||
|
|
; sld_storage_qualifier_inversion_mask_length ; 0 ; Untyped ;
|
||
|
|
; SLD_STORAGE_QUALIFIER_ADVANCED_CONDITION_ENTITY ; basic ; String ;
|
||
|
|
; SLD_STORAGE_QUALIFIER_PIPELINE ; 0 ; Signed Integer ;
|
||
|
|
; SLD_CREATE_MONITOR_INTERFACE ; 0 ; Signed Integer ;
|
||
|
|
; SLD_USE_JTAG_SIGNAL_ADAPTER ; 1 ; Signed Integer ;
|
||
|
|
+-------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+----------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1 ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 17 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 6 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_8bm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 6 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_k9m ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 6 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_hhm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0 ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 17 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 12 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_ikm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 5 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_ghm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 5 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_j9m ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0 ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 17 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 12 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_lcm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1 ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 12 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 6 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_0jm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 6 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_hhm ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Settings for Inferred Entity Instance: circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1 ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Parameter Name ; Value ; Type ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; LPM_WIDTHN ; 6 ; Untyped ;
|
||
|
|
; LPM_WIDTHD ; 4 ; Untyped ;
|
||
|
|
; LPM_NREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_DREPRESENTATION ; UNSIGNED ; Untyped ;
|
||
|
|
; LPM_PIPELINE ; 0 ; Untyped ;
|
||
|
|
; LPM_REMAINDERPOSITIVE ; TRUE ; Untyped ;
|
||
|
|
; MAXIMIZE_SPEED ; 5 ; Untyped ;
|
||
|
|
; CBXI_PARAMETER ; lpm_divide_k9m ; Untyped ;
|
||
|
|
; CARRY_CHAIN ; MANUAL ; Untyped ;
|
||
|
|
; OPTIMIZE_FOR_SPEED ; 5 ; Untyped ;
|
||
|
|
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
|
||
|
|
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
|
||
|
|
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
|
||
|
|
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
|
||
|
|
+------------------------+----------------+-----------------------------------------------------------------------------------------------------------------------+
|
||
|
|
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Port Connectivity Checks: "uart_tx:uart_tx_inst" ;
|
||
|
|
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||
|
|
; Port ; Type ; Severity ; Details ;
|
||
|
|
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||
|
|
; tx_vld ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
|
||
|
|
+--------+--------+----------+-------------------------------------------------------------------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Signal Tap Logic Analyzer Settings ;
|
||
|
|
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
|
||
|
|
; Instance Index ; Instance Name ; Trigger Input Width ; Data Input Width ; Sample Depth ; Segments ; Storage Qualifier Type ; Trigger Flow Control ; Trigger Conditions ; Advanced Trigger Conditions ; Trigger In Used ; Trigger Out Used ; Power-Up Trigger Enabled ;
|
||
|
|
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
|
||
|
|
; 0 ; auto_signaltap_0 ; 50 ; 50 ; 2048 ; 1 ; continuous ; sequential ; 1 ; 0 ; no ; no ; no ;
|
||
|
|
+----------------+------------------+---------------------+------------------+--------------+----------+------------------------+----------------------+--------------------+-----------------------------+-----------------+------------------+--------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-----------------------------------------------------+
|
||
|
|
; Post-Synthesis Netlist Statistics for Top Partition ;
|
||
|
|
+-----------------------+-----------------------------+
|
||
|
|
; Type ; Count ;
|
||
|
|
+-----------------------+-----------------------------+
|
||
|
|
; boundary_port ; 74 ;
|
||
|
|
; cycloneiii_ff ; 279 ;
|
||
|
|
; CLR ; 18 ;
|
||
|
|
; ENA ; 8 ;
|
||
|
|
; ENA CLR ; 94 ;
|
||
|
|
; ENA CLR SCLR ; 151 ;
|
||
|
|
; plain ; 8 ;
|
||
|
|
; cycloneiii_lcell_comb ; 1490 ;
|
||
|
|
; arith ; 463 ;
|
||
|
|
; 1 data inputs ; 1 ;
|
||
|
|
; 2 data inputs ; 223 ;
|
||
|
|
; 3 data inputs ; 239 ;
|
||
|
|
; normal ; 1027 ;
|
||
|
|
; 0 data inputs ; 49 ;
|
||
|
|
; 1 data inputs ; 32 ;
|
||
|
|
; 2 data inputs ; 436 ;
|
||
|
|
; 3 data inputs ; 102 ;
|
||
|
|
; 4 data inputs ; 408 ;
|
||
|
|
; ; ;
|
||
|
|
; Max LUT depth ; 41.60 ;
|
||
|
|
; Average LUT depth ; 20.97 ;
|
||
|
|
+-----------------------+-----------------------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------+
|
||
|
|
; Elapsed Time Per Partition ;
|
||
|
|
+----------------+--------------+
|
||
|
|
; Partition Name ; Elapsed Time ;
|
||
|
|
+----------------+--------------+
|
||
|
|
; Top ; 00:00:07 ;
|
||
|
|
+----------------+--------------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||
|
|
; Connections to In-System Debugging Instance "auto_signaltap_0" ;
|
||
|
|
+----------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+
|
||
|
|
; Name ; Type ; Status ; Partition Name ; Netlist Type Used ; Actual Connection ; Details ;
|
||
|
|
+----------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+
|
||
|
|
; byte_num[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; byte_num[0] ; N/A ;
|
||
|
|
; byte_num[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; byte_num[0] ; N/A ;
|
||
|
|
; byte_num[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; byte_num[1] ; N/A ;
|
||
|
|
; byte_num[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; byte_num[1] ; N/A ;
|
||
|
|
; instruction[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[0]~0 ; N/A ;
|
||
|
|
; instruction[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[0]~0 ; N/A ;
|
||
|
|
; instruction[10] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[10]~1 ; N/A ;
|
||
|
|
; instruction[10] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[10]~1 ; N/A ;
|
||
|
|
; instruction[11] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[11]~2 ; N/A ;
|
||
|
|
; instruction[11] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[11]~2 ; N/A ;
|
||
|
|
; instruction[12] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[12]~3 ; N/A ;
|
||
|
|
; instruction[12] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[12]~3 ; N/A ;
|
||
|
|
; instruction[13] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[13]~4 ; N/A ;
|
||
|
|
; instruction[13] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[13]~4 ; N/A ;
|
||
|
|
; instruction[14] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[14]~5 ; N/A ;
|
||
|
|
; instruction[14] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[14]~5 ; N/A ;
|
||
|
|
; instruction[15] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[15]~6 ; N/A ;
|
||
|
|
; instruction[15] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[15]~6 ; N/A ;
|
||
|
|
; instruction[16] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[16]~7 ; N/A ;
|
||
|
|
; instruction[16] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[16]~7 ; N/A ;
|
||
|
|
; instruction[17] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[17]~8 ; N/A ;
|
||
|
|
; instruction[17] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[17]~8 ; N/A ;
|
||
|
|
; instruction[18] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[18]~9 ; N/A ;
|
||
|
|
; instruction[18] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[18]~9 ; N/A ;
|
||
|
|
; instruction[19] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[19]~10 ; N/A ;
|
||
|
|
; instruction[19] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[19]~10 ; N/A ;
|
||
|
|
; instruction[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[1]~11 ; N/A ;
|
||
|
|
; instruction[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[1]~11 ; N/A ;
|
||
|
|
; instruction[20] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[20]~12 ; N/A ;
|
||
|
|
; instruction[20] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[20]~12 ; N/A ;
|
||
|
|
; instruction[21] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[21]~13 ; N/A ;
|
||
|
|
; instruction[21] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[21]~13 ; N/A ;
|
||
|
|
; instruction[22] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[22]~14 ; N/A ;
|
||
|
|
; instruction[22] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[22]~14 ; N/A ;
|
||
|
|
; instruction[23] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[23]~15 ; N/A ;
|
||
|
|
; instruction[23] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[23]~15 ; N/A ;
|
||
|
|
; instruction[2] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[2]~16 ; N/A ;
|
||
|
|
; instruction[2] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[2]~16 ; N/A ;
|
||
|
|
; instruction[3] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[3]~17 ; N/A ;
|
||
|
|
; instruction[3] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[3]~17 ; N/A ;
|
||
|
|
; instruction[4] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[4]~18 ; N/A ;
|
||
|
|
; instruction[4] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[4]~18 ; N/A ;
|
||
|
|
; instruction[5] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[5]~19 ; N/A ;
|
||
|
|
; instruction[5] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[5]~19 ; N/A ;
|
||
|
|
; instruction[6] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[6]~20 ; N/A ;
|
||
|
|
; instruction[6] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[6]~20 ; N/A ;
|
||
|
|
; instruction[7] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[7]~21 ; N/A ;
|
||
|
|
; instruction[7] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[7]~21 ; N/A ;
|
||
|
|
; instruction[8] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[8]~22 ; N/A ;
|
||
|
|
; instruction[8] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[8]~22 ; N/A ;
|
||
|
|
; instruction[9] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[9]~23 ; N/A ;
|
||
|
|
; instruction[9] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction[9]~23 ; N/A ;
|
||
|
|
; instruction_reg[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[0] ; N/A ;
|
||
|
|
; instruction_reg[0] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[0] ; N/A ;
|
||
|
|
; instruction_reg[10] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[10] ; N/A ;
|
||
|
|
; instruction_reg[10] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[10] ; N/A ;
|
||
|
|
; instruction_reg[11] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[11] ; N/A ;
|
||
|
|
; instruction_reg[11] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[11] ; N/A ;
|
||
|
|
; instruction_reg[12] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[12] ; N/A ;
|
||
|
|
; instruction_reg[12] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[12] ; N/A ;
|
||
|
|
; instruction_reg[13] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[13] ; N/A ;
|
||
|
|
; instruction_reg[13] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[13] ; N/A ;
|
||
|
|
; instruction_reg[14] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[14] ; N/A ;
|
||
|
|
; instruction_reg[14] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[14] ; N/A ;
|
||
|
|
; instruction_reg[15] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[15] ; N/A ;
|
||
|
|
; instruction_reg[15] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[15] ; N/A ;
|
||
|
|
; instruction_reg[16] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[16] ; N/A ;
|
||
|
|
; instruction_reg[16] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[16] ; N/A ;
|
||
|
|
; instruction_reg[17] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[17] ; N/A ;
|
||
|
|
; instruction_reg[17] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[17] ; N/A ;
|
||
|
|
; instruction_reg[18] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[18] ; N/A ;
|
||
|
|
; instruction_reg[18] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[18] ; N/A ;
|
||
|
|
; instruction_reg[19] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[19] ; N/A ;
|
||
|
|
; instruction_reg[19] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[19] ; N/A ;
|
||
|
|
; instruction_reg[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[1] ; N/A ;
|
||
|
|
; instruction_reg[1] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[1] ; N/A ;
|
||
|
|
; instruction_reg[20] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[20] ; N/A ;
|
||
|
|
; instruction_reg[20] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[20] ; N/A ;
|
||
|
|
; instruction_reg[21] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[21] ; N/A ;
|
||
|
|
; instruction_reg[21] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[21] ; N/A ;
|
||
|
|
; instruction_reg[22] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[22] ; N/A ;
|
||
|
|
; instruction_reg[22] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[22] ; N/A ;
|
||
|
|
; instruction_reg[23] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[23] ; N/A ;
|
||
|
|
; instruction_reg[23] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[23] ; N/A ;
|
||
|
|
; instruction_reg[2] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[2] ; N/A ;
|
||
|
|
; instruction_reg[2] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[2] ; N/A ;
|
||
|
|
; instruction_reg[3] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[3] ; N/A ;
|
||
|
|
; instruction_reg[3] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[3] ; N/A ;
|
||
|
|
; instruction_reg[4] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[4] ; N/A ;
|
||
|
|
; instruction_reg[4] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[4] ; N/A ;
|
||
|
|
; instruction_reg[5] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[5] ; N/A ;
|
||
|
|
; instruction_reg[5] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[5] ; N/A ;
|
||
|
|
; instruction_reg[6] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[6] ; N/A ;
|
||
|
|
; instruction_reg[6] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[6] ; N/A ;
|
||
|
|
; instruction_reg[7] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[7] ; N/A ;
|
||
|
|
; instruction_reg[7] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[7] ; N/A ;
|
||
|
|
; instruction_reg[8] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[8] ; N/A ;
|
||
|
|
; instruction_reg[8] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[8] ; N/A ;
|
||
|
|
; instruction_reg[9] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[9] ; N/A ;
|
||
|
|
; instruction_reg[9] ; pre-synthesis ; connected ; Top ; post-synthesis ; instruction_reg[9] ; N/A ;
|
||
|
|
; sys_clk ; pre-synthesis ; connected ; Top ; post-synthesis ; sys_clk ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|gnd ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~GND ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
; auto_signaltap_0|vcc ; post-fitting ; connected ; sld_signaltap:auto_signaltap_0 ; post-synthesis ; sld_signaltap:auto_signaltap_0|~VCC ; N/A ;
|
||
|
|
+----------------------+---------------+-----------+--------------------------------+-------------------+-------------------------------------+---------+
|
||
|
|
|
||
|
|
|
||
|
|
+-------------------------------+
|
||
|
|
; Analysis & Synthesis Messages ;
|
||
|
|
+-------------------------------+
|
||
|
|
Info: *******************************************************************
|
||
|
|
Info: Running Quartus Prime Analysis & Synthesis
|
||
|
|
Info: Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition
|
||
|
|
Info: Processing started: Thu Jun 20 16:27:13 2024
|
||
|
|
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga
|
||
|
|
Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance.
|
||
|
|
Info (20030): Parallel compilation is enabled and will use 4 of the 4 processors detected
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_tx.v
|
||
|
|
Info (12023): Found entity 1: uart_tx File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v Line: 2
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/uart_rx.v
|
||
|
|
Info (12023): Found entity 1: uart_rx File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_rx.v Line: 2
|
||
|
|
Info (12021): Found 0 design units, including 0 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/uart/param.v
|
||
|
|
Warning (10463): Verilog HDL Declaration warning at ws2812_ctrl.v(4): "bit" is SystemVerilog-2005 keyword File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v Line: 4
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v
|
||
|
|
Info (12023): Found entity 1: ws2812_ctrl File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_ctrl.v Line: 1
|
||
|
|
Warning (10463): Verilog HDL Declaration warning at ws2812_circuit.v(14): "bit" is SystemVerilog-2005 keyword File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v Line: 14
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v
|
||
|
|
Info (12023): Found entity 1: ws2812_circuit File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v Line: 1
|
||
|
|
Warning (10463): Verilog HDL Declaration warning at data_cfg.v(7): "bit" is SystemVerilog-2005 keyword File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v Line: 7
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v
|
||
|
|
Info (12023): Found entity 1: data_cfg File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/data_cfg.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v
|
||
|
|
Info (12023): Found entity 1: timer_decoder File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/timer.v
|
||
|
|
Info (12023): Found entity 1: timer File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v
|
||
|
|
Info (12023): Found entity 1: clock_circuit File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v
|
||
|
|
Info (12023): Found entity 1: pwm_beep File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/pwm_beep.v Line: 1
|
||
|
|
Warning (10229): Verilog HDL Expression warning at freq_select.v(12): truncated literal to match 6 bits File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 12
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/freq_select.v
|
||
|
|
Info (12023): Found entity 1: freq_select File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v
|
||
|
|
Info (12023): Found entity 1: beep_circuit File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/led/led_circuit.v
|
||
|
|
Info (12023): Found entity 1: led_circuit File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v Line: 1
|
||
|
|
Warning (12019): Can't analyze file -- file ../rtl/uart_tx.v is missing
|
||
|
|
Warning (12019): Can't analyze file -- file ../rtl/uart_top.v is missing
|
||
|
|
Warning (12019): Can't analyze file -- file ../rtl/uart_rx.v is missing
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/stark_machine.v
|
||
|
|
Info (12023): Found entity 1: stark_machine File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 1
|
||
|
|
Warning (12019): Can't analyze file -- file ../rtl/param.v is missing
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/key_filter.v
|
||
|
|
Info (12023): Found entity 1: key_filter File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/key_filter.v Line: 2
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/instr_decode.v
|
||
|
|
Info (12023): Found entity 1: instr_decode File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/instr_decode.v Line: 1
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file /users/stark-lin/desktop/agi_fpga/hardware/rtl/circuit_arb.v
|
||
|
|
Info (12023): Found entity 1: circuit_arb File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v Line: 1
|
||
|
|
Info (12127): Elaborating entity "stark_machine" for the top level hierarchy
|
||
|
|
Info (12128): Elaborating entity "uart_rx" for hierarchy "uart_rx:uart_rx_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 57
|
||
|
|
Info (12128): Elaborating entity "uart_tx" for hierarchy "uart_tx:uart_tx_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 66
|
||
|
|
Info (12128): Elaborating entity "instr_decode" for hierarchy "instr_decode:instr_decode_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 73
|
||
|
|
Info (12128): Elaborating entity "circuit_arb" for hierarchy "circuit_arb:circuit_arb_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 87
|
||
|
|
Info (12128): Elaborating entity "led_circuit" for hierarchy "circuit_arb:circuit_arb_inst|led_circuit:led_circuit_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v Line: 32
|
||
|
|
Warning (10230): Verilog HDL assignment warning at led_circuit.v(39): truncated value with size 32 to match size of target (28) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/led/led_circuit.v Line: 39
|
||
|
|
Info (12128): Elaborating entity "beep_circuit" for hierarchy "circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v Line: 41
|
||
|
|
Info (12128): Elaborating entity "freq_select" for hierarchy "circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v Line: 19
|
||
|
|
Warning (10270): Verilog HDL Case Statement warning at freq_select.v(116): incomplete case statement has no default case item File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10264): Verilog HDL Case Statement information at freq_select.v(116): all case item expressions in this case statement are onehot File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Warning (10240): Verilog HDL Always Construct warning at freq_select.v(116): inferring latch(es) for variable "note", which holds its previous value in one or more paths through the always construct File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[0]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[1]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[2]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[3]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[4]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (10041): Inferred latch for "note[5]" at freq_select.v(116) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Info (12128): Elaborating entity "pwm_beep" for hierarchy "circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|pwm_beep:pwm_beep_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/beep_circuit.v Line: 27
|
||
|
|
Info (12128): Elaborating entity "clock_circuit" for hierarchy "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v Line: 51
|
||
|
|
Info (12128): Elaborating entity "timer" for hierarchy "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v Line: 24
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer.v(79): truncated value with size 32 to match size of target (5) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 79
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer.v(80): truncated value with size 32 to match size of target (6) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer.v(81): truncated value with size 32 to match size of target (6) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 81
|
||
|
|
Info (12128): Elaborating entity "timer_decoder" for hierarchy "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/clock_circuit.v Line: 37
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(80): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 80
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(81): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 81
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(82): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 82
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(83): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 83
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(84): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 84
|
||
|
|
Warning (10230): Verilog HDL assignment warning at timer_decoder.v(85): truncated value with size 32 to match size of target (4) File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 85
|
||
|
|
Info (12128): Elaborating entity "ws2812_circuit" for hierarchy "circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/circuit_arb.v Line: 60
|
||
|
|
Info (12128): Elaborating entity "ws2812_ctrl" for hierarchy "circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|ws2812_ctrl:ws2812_ctrl_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v Line: 27
|
||
|
|
Info (12128): Elaborating entity "data_cfg" for hierarchy "circuit_arb:circuit_arb_inst|ws2812_circuit:ws2812_circuit_inst|data_cfg:data_cfg_inst" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/ws2812/ws2812_circuit.v Line: 34
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_sa24.tdf
|
||
|
|
Info (12023): Found entity 1: altsyncram_sa24 File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/altsyncram_sa24.tdf Line: 27
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_rsc.tdf
|
||
|
|
Info (12023): Found entity 1: mux_rsc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/mux_rsc.tdf Line: 22
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_dvf.tdf
|
||
|
|
Info (12023): Found entity 1: decode_dvf File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/decode_dvf.tdf Line: 22
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_fgi.tdf
|
||
|
|
Info (12023): Found entity 1: cntr_fgi File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_fgi.tdf Line: 27
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_sgc.tdf
|
||
|
|
Info (12023): Found entity 1: cmpr_sgc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_sgc.tdf Line: 22
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_g9j.tdf
|
||
|
|
Info (12023): Found entity 1: cntr_g9j File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_g9j.tdf Line: 25
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_egi.tdf
|
||
|
|
Info (12023): Found entity 1: cntr_egi File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_egi.tdf Line: 27
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_rgc.tdf
|
||
|
|
Info (12023): Found entity 1: cmpr_rgc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_rgc.tdf Line: 22
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cntr_23j.tdf
|
||
|
|
Info (12023): Found entity 1: cntr_23j File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cntr_23j.tdf Line: 27
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/cmpr_ngc.tdf
|
||
|
|
Info (12023): Found entity 1: cmpr_ngc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/cmpr_ngc.tdf Line: 22
|
||
|
|
Info (12033): Analysis and Synthesis generated Signal Tap or debug node instance "auto_signaltap_0"
|
||
|
|
Info (11170): Starting IP generation for the debug fabric: alt_sld_fab.
|
||
|
|
Info (11172): 2024.06.20.16:27:48 Progress: Loading sldbacf2b6c/alt_sld_fab_wrapper_hw.tcl
|
||
|
|
Info (11172): Alt_sld_fab.alt_sld_fab: SLD fabric agents which did not specify prefer_host were connected to JTAG
|
||
|
|
Info (11172): Alt_sld_fab: Generating alt_sld_fab "alt_sld_fab" for QUARTUS_SYNTH
|
||
|
|
Info (11172): Alt_sld_fab: "alt_sld_fab" instantiated alt_sld_fab "alt_sld_fab"
|
||
|
|
Info (11172): Presplit: "alt_sld_fab" instantiated altera_super_splitter "presplit"
|
||
|
|
Info (11172): Splitter: "alt_sld_fab" instantiated altera_sld_splitter "splitter"
|
||
|
|
Info (11172): Sldfabric: "alt_sld_fab" instantiated altera_sld_jtag_hub "sldfabric"
|
||
|
|
Info (11172): Ident: "alt_sld_fab" instantiated altera_connection_identification_hub "ident"
|
||
|
|
Info (11172): Alt_sld_fab: Done "alt_sld_fab" with 6 modules, 6 files
|
||
|
|
Info (11171): Finished IP generation for the debug fabric: alt_sld_fab.
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/alt_sld_fab.v
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/alt_sld_fab.v Line: 9
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab.v Line: 9
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_ident File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_ident.sv Line: 33
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_presplit File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_presplit.sv Line: 3
|
||
|
|
Info (12021): Found 2 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd
|
||
|
|
Info (12022): Found design unit 1: alt_sld_fab_alt_sld_fab_sldfabric-rtl File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 102
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_sldfabric File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_sldfabric.vhd Line: 11
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv
|
||
|
|
Info (12023): Found entity 1: alt_sld_fab_alt_sld_fab_splitter File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/ip/sldbacf2b6c/submodules/alt_sld_fab_alt_sld_fab_splitter.sv Line: 3
|
||
|
|
Info (278001): Inferred 10 megafunctions from design logic
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|Mod1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 81
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Mod2" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 85
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Div2" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 84
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|Div0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 79
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Div0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 80
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Mod0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 81
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|Mod0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|Div1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Div1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 82
|
||
|
|
Info (278004): Inferred divider/modulo megafunction ("lpm_divide") from the following logic: "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|Mod1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 83
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 81
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod1" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 81
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "17"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "6"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_8bm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_8bm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_8bm.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_tlh.tdf
|
||
|
|
Info (12023): Found entity 1: sign_div_unsign_tlh File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_tlh.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_e7f.tdf
|
||
|
|
Info (12023): Found entity 1: alt_u_div_e7f File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_e7f.tdf Line: 26
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_7pc.tdf
|
||
|
|
Info (12023): Found entity 1: add_sub_7pc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_7pc.tdf Line: 22
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/add_sub_8pc.tdf
|
||
|
|
Info (12023): Found entity 1: add_sub_8pc File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/add_sub_8pc.tdf Line: 22
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 85
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod2" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 85
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "6"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "4"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_k9m.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_k9m File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_k9m.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_9kh.tdf
|
||
|
|
Info (12023): Found entity 1: sign_div_unsign_9kh File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_9kh.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_64f.tdf
|
||
|
|
Info (12023): Found entity 1: alt_u_div_64f File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 26
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 84
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div2" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 84
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "6"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "4"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_hhm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_hhm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_hhm.tdf Line: 24
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 79
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div0" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 79
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "17"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "12"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_ikm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_ikm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ikm.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_anh.tdf
|
||
|
|
Info (12023): Found entity 1: sign_div_unsign_anh File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_anh.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_8af.tdf
|
||
|
|
Info (12023): Found entity 1: alt_u_div_8af File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_8af.tdf Line: 26
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 80
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 80
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "5"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "4"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_ghm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_ghm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_ghm.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_8kh.tdf
|
||
|
|
Info (12023): Found entity 1: sign_div_unsign_8kh File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_8kh.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_44f.tdf
|
||
|
|
Info (12023): Found entity 1: alt_u_div_44f File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf Line: 26
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 81
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer_decoder.v Line: 81
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "5"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "4"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_j9m.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_j9m File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_j9m.tdf Line: 24
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Mod0" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "17"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "12"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_lcm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_lcm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_lcm.tdf Line: 24
|
||
|
|
Info (12130): Elaborated megafunction instantiation "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (12133): Instantiated megafunction "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer:timer_inst|lpm_divide:Div1" with the following parameter: File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/digit_led/timer.v Line: 80
|
||
|
|
Info (12134): Parameter "LPM_WIDTHN" = "12"
|
||
|
|
Info (12134): Parameter "LPM_WIDTHD" = "6"
|
||
|
|
Info (12134): Parameter "LPM_NREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12134): Parameter "LPM_DREPRESENTATION" = "UNSIGNED"
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/lpm_divide_0jm.tdf
|
||
|
|
Info (12023): Found entity 1: lpm_divide_0jm File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/lpm_divide_0jm.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/sign_div_unsign_olh.tdf
|
||
|
|
Info (12023): Found entity 1: sign_div_unsign_olh File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/sign_div_unsign_olh.tdf Line: 24
|
||
|
|
Info (12021): Found 1 design units, including 1 entities, in source file db/alt_u_div_47f.tdf
|
||
|
|
Info (12023): Found entity 1: alt_u_div_47f File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_47f.tdf Line: 26
|
||
|
|
Info (13025): Duplicate LATCH primitives merged into single LATCH primitive
|
||
|
|
Info (13026): Duplicate LATCH primitive "circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[5]" merged with LATCH primitive "circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[1]" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Warning (13012): Latch circuit_arb:circuit_arb_inst|beep_circuit:beep_circuit_inst|freq_select:freq_select_inst|note[1] has unsafe behavior File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/beep/freq_select.v Line: 116
|
||
|
|
Warning (13013): Ports D and ENA on the latch are fed by the same signal instruction_reg[0] File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 27
|
||
|
|
Info (13000): Registers with preset signals will power-up high File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/uart/uart_tx.v Line: 11
|
||
|
|
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
|
||
|
|
Warning (13024): Output pins are stuck at VCC or GND
|
||
|
|
Warning (13410): Pin "seg_led[7]" is stuck at VCC File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/rtl/stark_machine.v Line: 9
|
||
|
|
Info (286031): Timing-Driven Synthesis is running on partition "Top"
|
||
|
|
Info (17016): Found the following redundant logic cells in design
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div0|lpm_divide_ghm:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider|add_sub_3_result_int[0]~8" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf Line: 41
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider|add_sub_4_result_int[0]~0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf Line: 46
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod0|lpm_divide_j9m:auto_generated|sign_div_unsign_8kh:divider|alt_u_div_44f:divider|add_sub_3_result_int[0]~8" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_44f.tdf Line: 41
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider|add_sub_3_result_int[0]~8" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 41
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Div1|lpm_divide_hhm:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider|add_sub_4_result_int[0]~10" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 46
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider|add_sub_5_result_int[0]~0" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 51
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider|add_sub_3_result_int[0]~8" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 41
|
||
|
|
Info (17048): Logic cell "circuit_arb:circuit_arb_inst|clock_circuit:clock_circuit_inst|timer_decoder:timer_decoder_inst|lpm_divide:Mod1|lpm_divide_k9m:auto_generated|sign_div_unsign_9kh:divider|alt_u_div_64f:divider|add_sub_4_result_int[0]~10" File: C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/db/alt_u_div_64f.tdf Line: 46
|
||
|
|
Info (144001): Generated suppressed messages file C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg
|
||
|
|
Info (35024): Successfully connected in-system debug instance "auto_signaltap_0" to all 133 required data inputs, trigger inputs, acquisition clocks, and dynamic pins
|
||
|
|
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
|
||
|
|
Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
|
||
|
|
Info (21057): Implemented 2905 device resources after synthesis - the final resource count might be different
|
||
|
|
Info (21058): Implemented 6 input pins
|
||
|
|
Info (21059): Implemented 22 output pins
|
||
|
|
Info (21061): Implemented 2826 logic cells
|
||
|
|
Info (21064): Implemented 50 RAM segments
|
||
|
|
Info: Quartus Prime Analysis & Synthesis was successful. 0 errors, 25 warnings
|
||
|
|
Info: Peak virtual memory: 4860 megabytes
|
||
|
|
Info: Processing ended: Thu Jun 20 16:28:19 2024
|
||
|
|
Info: Elapsed time: 00:01:06
|
||
|
|
Info: Total CPU time (on all processors): 00:01:31
|
||
|
|
|
||
|
|
|
||
|
|
+------------------------------------------+
|
||
|
|
; Analysis & Synthesis Suppressed Messages ;
|
||
|
|
+------------------------------------------+
|
||
|
|
The suppressed messages can be found in C:/Users/Stark-lin/Desktop/agi_fpga/hardware/prj/output_files/agi_fpga.map.smsg.
|
||
|
|
|
||
|
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|