agi_fpga/hardware/rtl/digit_led/timer.v

module timer(
    input   wire        sys_clk     ,
    input   wire        sys_rst_n   ,
    input   wire [1: 0] dev_id      ,
    input   wire [3: 0] opcode      ,

    output  wire [4: 0] hour        ,
    output  wire [5: 0] min         ,
    output  wire [5: 0] sec
);
parameter MAX = 28'd50_000_000;
parameter DAY = 17'd86400;
reg [27: 0] cnt_s;//秒计数寄存器
wire        add_cnt_s;
wire        end_cnt_s;

reg [16: 0] cnt_day;//一天多少秒计数寄存器
wire        add_cnt_day;
wire        end_cnt_day;
reg         start_flag;
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        start_flag <= 1'b0;
    end 
    else if((dev_id == 2'd2) && (opcode == 4'b0001))begin
        start_flag <= 1'b0;
    end 
    else if((dev_id == 2'd2) && (opcode == 4'b0010))begin
        start_flag <= 1'b1;
    end 
    else begin
        start_flag <= start_flag;
    end 
end 
//秒计数器设计
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_s <= 28'd0;
    end 
    else if((dev_id == 2'd2) && (opcode == 4'b0001))begin
        cnt_s <= 28'd0;
    end 
    else if(add_cnt_s)begin
        if(end_cnt_s)begin
            cnt_s <= 28'd0;
        end 
        else begin
            cnt_s <= cnt_s + 1'd1;
        end 
    end   
    else begin
        cnt_s <= cnt_s;
    end   
end
assign add_cnt_s = start_flag;
assign end_cnt_s = add_cnt_s && (cnt_s == MAX - 1'd1);
//天计数器设计
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_day <= 17'd0;
    end 
    else if((dev_id == 2'd2) && (opcode == 4'b0001))begin
        cnt_day <= 17'd0;
    end 
    else if(add_cnt_day)begin
        if(end_cnt_day)begin
            cnt_day <= 17'd0;
        end 
        else begin
            cnt_day <= cnt_day + 1'd1;
        end 
    end 
    else begin
        cnt_day <= cnt_day;
    end 
end 
assign add_cnt_day = end_cnt_s;
assign end_cnt_day = add_cnt_day && (cnt_day == DAY - 1'd1);
assign hour = cnt_day / 3600;//解析小时
assign min  = cnt_day % 3600 / 60;//解析分钟
assign sec  = cnt_day % 60;//解析秒
endmodule