agi_fpga/hardware/rtl/stark_machine.v

module stark_machine(
    input           sys_clk     ,
    input           sys_rst_n   ,
    input           rx          ,

    output          tx          ,
    output  [3: 0]  led         ,
	output          beep        ,
    output  [7: 0]  seg_led     ,
    output  [5: 0]  sel_led     ,
    output          dout
);
reg [23: 0] instruction_reg;//指令寄存器
wire  [7: 0] opcode;//操作码
wire  [7: 0] slave_id;//电路id
wire  [7: 0] data;//数据
wire  [7: 0] rx_byte;//接受的数据
wire         rx_vld;//串转并有效
wire [23: 0] instruction;//指令
reg [1: 0]   byte_num;//字节计数器
wire         tx_vld;
// assign instruction = 24'h01020f;
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        instruction_reg <= 24'h000000;
    end 
    else if(rx_vld)begin
        instruction_reg <= {instruction_reg[15: 0], rx_byte};
    end 
    else begin
        instruction_reg <= instruction_reg;
    end 
end 
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        byte_num <= 2'd0;
    end 
    else if(rx_vld)begin
        byte_num <= byte_num + 1'd1;
    end 
    else if(byte_num == 2'd3)begin
        byte_num <= 2'd0;
    end
    else begin
        byte_num <= byte_num;
    end 
end 
assign instruction = (byte_num == 2'd3) ? instruction_reg: 24'h000000;
//接受上位机
uart_rx     uart_rx_inst(
.sys_clk        (sys_clk),
.sys_rst_n      (sys_rst_n),
.rx_din         (rx),//数据串行输入

.rx_dout        (rx_byte),//数据并行输出
.rx_vld         (rx_vld)//输出信号有效
); 
uart_tx     uart_tx_inst(
.sys_clk        (sys_clk),
.sys_rst_n      (sys_rst_n),
.tx_din         (rx_byte),//并行输入，接受模块传入
.rx_vld         (rx_vld),//接受模块，串转并有效信号

.tx_vld         (tx_vld),
.tx_dout        (tx)//串行输出
);
instr_decode instr_decode_inst(
.instruction    (instruction),//指令
    
.opcode         (opcode),//操作码
.slave_id       (slave_id),//电路id
.data           (data) //数据
 );
 
circuit_arb circuit_arb_inst(//仲裁电路
.sys_clk        (sys_clk),
.sys_rst_n      (sys_rst_n),
.slave_id       (slave_id),
.opcode         (opcode),
.data           (data),
    
.led            (led),
.beep           (beep),
.seg_led        (seg_led),
.sel_led        (sel_led),
.dout           (dout)
);
endmodule