set tool_name "ModelSim-Altera (Verilog)"
set corner_file_list {
    {{"Slow -8 1.2V 85 Model"} {agi_fpga_8_1200mv_85c_slow.vo agi_fpga_8_1200mv_85c_v_slow.sdo}}
    {{"Slow -8 1.2V 0 Model"} {agi_fpga_8_1200mv_0c_slow.vo agi_fpga_8_1200mv_0c_v_slow.sdo}}
    {{"Fast -M 1.2V 0 Model"} {agi_fpga_min_1200mv_0c_fast.vo agi_fpga_min_1200mv_0c_v_fast.sdo}}
}