--sign_div_unsign DEN_REPRESENTATION="UNSIGNED" DEN_WIDTH=6 LPM_PIPELINE=0 MAXIMIZE_SPEED=5 NUM_REPRESENTATION="UNSIGNED" NUM_WIDTH=17 SKIP_BITS=0 denominator numerator quotient remainder --VERSION_BEGIN 18.1 cbx_cycloneii 2018:09:12:13:04:24:SJ cbx_lpm_abs 2018:09:12:13:04:24:SJ cbx_lpm_add_sub 2018:09:12:13:04:24:SJ cbx_lpm_divide 2018:09:12:13:04:24:SJ cbx_mgl 2018:09:12:13:10:36:SJ cbx_nadder 2018:09:12:13:04:24:SJ cbx_stratix 2018:09:12:13:04:24:SJ cbx_stratixii 2018:09:12:13:04:24:SJ cbx_util_mgl 2018:09:12:13:04:24:SJ VERSION_END -- Copyright (C) 2018 Intel Corporation. All rights reserved. -- Your use of Intel Corporation's design tools, logic functions -- and other software and tools, and its AMPP partner logic -- functions, and any output files from any of the foregoing -- (including device programming or simulation files), and any -- associated documentation or information are expressly subject -- to the terms and conditions of the Intel Program License -- Subscription Agreement, the Intel Quartus Prime License Agreement, -- the Intel FPGA IP License Agreement, or other applicable license -- agreement, including, without limitation, that your use is for -- the sole purpose of programming logic devices manufactured by -- Intel and sold by Intel or its authorized distributors. Please -- refer to the applicable agreement for further details. FUNCTION alt_u_div_e7f (denominator[5..0], numerator[16..0]) RETURNS ( quotient[16..0], remainder[5..0]); --synthesis_resources = lut 110 SUBDESIGN sign_div_unsign_tlh ( denominator[5..0] : input; numerator[16..0] : input; quotient[16..0] : output; remainder[5..0] : output; ) VARIABLE divider : alt_u_div_e7f; norm_num[16..0] : WIRE; protect_quotient[16..0] : WIRE; protect_remainder[5..0] : WIRE; BEGIN divider.denominator[] = denominator[]; divider.numerator[] = norm_num[]; norm_num[] = numerator[]; protect_quotient[] = divider.quotient[]; protect_remainder[] = divider.remainder[]; quotient[] = protect_quotient[]; remainder[] = protect_remainder[]; END; --VALID FILE