Flow report for agi_fpga Thu Jun 20 16:28:50 2024 Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Flow Summary 3. Flow Settings 4. Flow Non-Default Global Settings 5. Flow Elapsed Time 6. Flow OS Summary 7. Flow Log 8. Flow Messages 9. Flow Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2018 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel FPGA IP License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Flow Summary ; +------------------------------------+---------------------------------------------+ ; Flow Status ; Successful - Thu Jun 20 16:28:50 2024 ; ; Quartus Prime Version ; 18.1.0 Build 625 09/12/2018 SJ Lite Edition ; ; Revision Name ; agi_fpga ; ; Top-level Entity Name ; stark_machine ; ; Family ; Cyclone IV E ; ; Device ; EP4CE6F17C8 ; ; Timing Models ; Final ; ; Total logic elements ; 2,715 / 6,272 ( 43 % ) ; ; Total combinational functions ; 2,124 / 6,272 ( 34 % ) ; ; Dedicated logic registers ; 1,320 / 6,272 ( 21 % ) ; ; Total registers ; 1320 ; ; Total pins ; 24 / 180 ( 13 % ) ; ; Total virtual pins ; 0 ; ; Total memory bits ; 102,400 / 276,480 ( 37 % ) ; ; Embedded Multiplier 9-bit elements ; 0 / 30 ( 0 % ) ; ; Total PLLs ; 0 / 2 ( 0 % ) ; +------------------------------------+---------------------------------------------+ +-----------------------------------------+ ; Flow Settings ; +-------------------+---------------------+ ; Option ; Setting ; +-------------------+---------------------+ ; Start date & time ; 06/20/2024 16:27:14 ; ; Main task ; Compilation ; ; Revision Name ; agi_fpga ; +-------------------+---------------------+ +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Flow Non-Default Global Settings ; +-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+ ; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; +-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+ ; COMPILER_SIGNATURE_ID ; 118933435750018.171887203417796 ; -- ; -- ; -- ; ; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; ; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; ; EDA_TIME_SCALE ; 1 ps ; -- ; -- ; eda_simulation ; ; ENABLE_SIGNALTAP ; On ; -- ; -- ; -- ; ; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; ; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; ; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; ; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ; ; OUTPUT_IO_TIMING_FAR_END_VMEAS ; Half Signal Swing ; -- ; -- ; -- ; ; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ; ; OUTPUT_IO_TIMING_NEAR_END_VMEAS ; Half Vccio ; -- ; -- ; -- ; ; PARTITION_COLOR ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ; ; PARTITION_FITTER_PRESERVATION_LEVEL ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ; ; PARTITION_NETLIST_TYPE ; -- (Not supported for targeted family) ; -- ; stark_machine ; Top ; ; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; ; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; ; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ; SLD_FILE ; db/stp1_auto_stripped.stp ; -- ; -- ; -- ; ; SLD_NODE_CREATOR_ID ; 110 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_ENTITY_NAME ; sld_signaltap ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_RAM_BLOCK_TYPE=AUTO ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_DATA_BITS=50 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_BITS=50 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_BITS=50 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_NODE_INFO=805334528 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_POWER_UP_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INVERSION_MASK_LENGTH=175 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SEGMENT_SIZE=2048 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ATTRIBUTE_MEM_MODE=OFF ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_FLOW_USE_GENERATED=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_STATE_BITS=11 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_BUFFER_FULL_STOP=1 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_CURRENT_RESOURCE_WIDTH=1 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_INCREMENTAL_ROUTING=1 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL=1 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_SAMPLE_DEPTH=2048 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_IN_ENABLED=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_RAM_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_COUNTER_PIPELINE=0 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ADVANCED_TRIGGER_ENTITY=basic,1, ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_TRIGGER_LEVEL_PIPELINE=1 ; -- ; -- ; auto_signaltap_0 ; ; SLD_NODE_PARAMETER_ASSIGNMENT ; SLD_ENABLE_ADVANCED_TRIGGER=0 ; -- ; -- ; auto_signaltap_0 ; ; TOP_LEVEL_ENTITY ; stark_machine ; agi_fpga ; -- ; -- ; ; USE_SIGNALTAP_FILE ; output_files/stp1.stp ; -- ; -- ; -- ; +-------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------+---------------+------------------+ +--------------------------------------------------------------------------------------------------------------------------+ ; Flow Elapsed Time ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ ; Analysis & Synthesis ; 00:01:03 ; 1.0 ; 4860 MB ; 00:01:29 ; ; Fitter ; 00:00:13 ; 1.1 ; 5519 MB ; 00:00:06 ; ; Assembler ; 00:00:02 ; 1.0 ; 4680 MB ; 00:00:01 ; ; Timing Analyzer ; 00:00:04 ; 1.3 ; 4779 MB ; 00:00:02 ; ; EDA Netlist Writer ; 00:00:05 ; 1.0 ; 4675 MB ; 00:00:03 ; ; Total ; 00:01:27 ; -- ; -- ; 00:01:41 ; +----------------------+--------------+-------------------------+---------------------+------------------------------------+ +------------------------------------------------------------------------------------+ ; Flow OS Summary ; +----------------------+------------------+------------+------------+----------------+ ; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; +----------------------+------------------+------------+------------+----------------+ ; Analysis & Synthesis ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ; ; Fitter ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ; ; Assembler ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ; ; Timing Analyzer ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ; ; EDA Netlist Writer ; DESKTOP-RQPS28G ; Windows 10 ; 10.0 ; x86_64 ; +----------------------+------------------+------------+------------+----------------+ ------------ ; Flow Log ; ------------ quartus_map --read_settings_files=on --write_settings_files=off agi_fpga -c agi_fpga quartus_fit --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga quartus_asm --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga quartus_sta agi_fpga -c agi_fpga quartus_eda --read_settings_files=off --write_settings_files=off agi_fpga -c agi_fpga