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7 lines
356 B
Plaintext
7 lines
356 B
Plaintext
set tool_name "ModelSim-Altera (Verilog)"
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set corner_file_list {
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{{"Slow -8 1.2V 85 Model"} {agi_fpga_8_1200mv_85c_slow.vo agi_fpga_8_1200mv_85c_v_slow.sdo}}
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{{"Slow -8 1.2V 0 Model"} {agi_fpga_8_1200mv_0c_slow.vo agi_fpga_8_1200mv_0c_v_slow.sdo}}
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{{"Fast -M 1.2V 0 Model"} {agi_fpga_min_1200mv_0c_fast.vo agi_fpga_min_1200mv_0c_v_fast.sdo}}
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}
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