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12 lines
341 B
Verilog

module instr_decode(
input [23: 0] instruction ,//指令
output [7: 0] opcode ,//操作码
output [7: 0] slave_id ,//电路id
output [7: 0] data //数据
);
assign slave_id = instruction[23:16];
assign opcode = instruction[15: 8];
assign data = instruction[7: 0];
endmodule