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67 lines
1.6 KiB
Verilog
67 lines
1.6 KiB
Verilog
module led_circuit(
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input sys_clk ,
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input sys_rst_n ,
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input [3: 0] opcode ,
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input [3: 0] data ,
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input [1: 0] dev_id ,//设备地址
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output reg [3: 0] led
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);
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parameter MAX = 28'd50_000_000;
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reg [27: 0] cnt_1s;
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wire end_cnt;
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wire add_cnt;
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reg flag ;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag <= 1'b0;
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end
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else if((dev_id == 2'd0) && (opcode == 4'b0100))begin
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flag <= 1'b1;
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end
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else if((dev_id == 2'd0) && (opcode == 4'b0001 || opcode == 4'b0010))begin
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flag <= 1'b0;
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end
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else begin
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flag <= flag;
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end
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end
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//1s计数器
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_1s <= 28'd0;
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end
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else if(add_cnt)begin
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if(end_cnt)begin
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cnt_1s <= 28'd0;
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end
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else begin
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cnt_1s <= cnt_1s + 1;
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end
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end
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else begin
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cnt_1s <= cnt_1s;
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end
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end
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assign add_cnt = flag;
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assign end_cnt = add_cnt && (cnt_1s == MAX - 1);
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led <= 4'b0000;
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end
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else if((dev_id == 2'd0) && (opcode == 4'b0001))begin
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led <= 4'b0000;
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end
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else if((dev_id == 2'd0) && (opcode == 4'b0010 || opcode == 4'b0100 ))begin
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led <= data;
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end
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else if(end_cnt)begin
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led <= {led[2: 0], led[3]};
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end
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else begin
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led <= led;
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end
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end
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endmodule
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