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module ws2812_ctrl(
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input sys_clk ,//系统时钟，50MHz
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input sys_rst_n ,//系统复位，下降沿有效
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input bit ,//data_cfg给的bit
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input [3: 0] opcode ,
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input [3: 0] data ,
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input [1: 0] dev_id ,//设备地址
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output reg [4: 0] bit_num ,//bit计数寄存器
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output reg [6: 0] led_num ,//led计数寄存器
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output reg [1: 0] frame ,//帧
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output dout//点阵输出
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);
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parameter T0H = 4'd13,//0高电平时间
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T0L = 5'd30,//0低电平时间
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T1H = 5'd30,//1高电平时间
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T1L = 5'd30,//1低电平时间
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RST = 26'd5_000_000;//复位时间
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parameter BIT = 5'd24,
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LED = 7'd64;
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reg [5: 0] cnt_0;//0bit计数寄存器
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wire add_cnt_0;
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wire end_cnt_0;
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reg [5: 0] cnt_1;//1bit计数寄存器
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wire add_cnt_1;
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wire end_cnt_1;
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reg [25: 0] cnt_rst;//复位计数寄存器
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wire add_cnt_rst;
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wire end_cnt_rst;
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//bit计数寄存器
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wire add_bit_num;
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wire end_bit_num;
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//led计数寄存器
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wire add_led_num;
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wire end_led_num;
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reg rst_flag ;//复位标志
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reg start_flag ;
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//开始信号
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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start_flag <= 1'b0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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start_flag <= 1'b0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0010))begin
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start_flag <= 1'b1;
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end
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else begin
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start_flag <= start_flag;
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end
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end
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//bit0计数器设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_0 <= 6'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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cnt_0 <= 6'd0;
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end
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else if(add_cnt_0)begin
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if(end_cnt_0)begin
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cnt_0 <= 6'd0;
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end
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else begin
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cnt_0 <= cnt_0 + 1'd1;
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end
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end
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else begin
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cnt_0 <= cnt_0;
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end
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end
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assign add_cnt_0 = start_flag && ~bit && ~rst_flag;
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assign end_cnt_0 = add_cnt_0 && cnt_0 == T0H + T0L - 1'd1;
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//bit1计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_1 <= 6'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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cnt_1 <= 6'd0;
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end
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else if(add_cnt_1)begin
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if(end_cnt_1)begin
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cnt_1 <= 6'd0;
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end
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else begin
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cnt_1 <= cnt_1 + 1'd1;
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end
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end
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else begin
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cnt_1 <= cnt_1;
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end
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end
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assign add_cnt_1 = start_flag && bit && ~rst_flag;
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assign end_cnt_1 = add_cnt_1 && cnt_1 == T1H + T1L - 1'd1;
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//bit计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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bit_num <= 5'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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bit_num <= 5'd0;
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end
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else if(add_bit_num)begin
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if(end_bit_num)begin
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bit_num <= 5'd0;
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end
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else begin
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bit_num <= bit_num + 1'd1;
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end
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end
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else begin
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bit_num <= bit_num;
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end
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end
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assign add_bit_num = end_cnt_0 || end_cnt_1;//0bit或者1bit结束，bit计数器加1
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assign end_bit_num = add_bit_num && bit_num == BIT - 1'd1;
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//led计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led_num <= 7'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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led_num <= 7'd0;
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end
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else if(add_led_num)begin
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if(end_led_num)begin
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led_num <= 7'd0;
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end
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else begin
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led_num <= led_num + 1'd1;
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end
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end
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else begin
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led_num <= led_num;
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end
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end
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assign add_led_num = end_bit_num;
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assign end_led_num = add_led_num && led_num == LED - 1'd1;
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//rst_flag约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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rst_flag <= 1'b0;
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end
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else if(end_led_num)begin
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rst_flag <= 1'b1;
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end
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else if(end_cnt_rst)begin
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rst_flag <= 1'b0;
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end
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else begin
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rst_flag <= rst_flag;
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end
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end
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//复位计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_rst <= 26'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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cnt_rst <= 26'd0;
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end
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else if(add_cnt_rst)begin
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if(end_cnt_rst)begin
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cnt_rst <= 26'd0;
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end
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else begin
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cnt_rst <= cnt_rst + 1'd1;
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end
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end
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else begin
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cnt_rst <= cnt_rst;
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end
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end
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assign add_cnt_rst = rst_flag;
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assign end_cnt_rst = add_cnt_rst && cnt_rst == RST - 1'd1;
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//frame约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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frame <= 2'd0;
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end
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else if((dev_id == 2'd3) && (opcode == 4'b0001))begin
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frame <= 2'd0;
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end
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else if((frame == 2'd3) && (end_cnt_rst))begin
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frame <= 2'd0;
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end
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else if(end_cnt_rst)begin
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frame <= frame + 1'd1;
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end
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else begin
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frame <= frame;
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end
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end
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///////////////输出///////////////
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assign dout = (rst_flag == 0) ? (((bit == 0 && cnt_0 < T0H) ? 1'b1 : 1'b0) | ((bit == 1 && cnt_1 < T1H) ? 1'b1 : 1'b0)): 1'b0;
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endmodule |