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28 lines
564 B
Verilog
28 lines
564 B
Verilog
module beep_circuit(
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input sys_clk ,
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input sys_rst_n ,
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input [1: 0] dev_id ,
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input [3: 0] opcode ,
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input [3: 0] data ,
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output beep
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);
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wire pwm;
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freq_select freq_select_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.dev_id (dev_id),
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.opcode (opcode),
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.data (data),
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.pwm (pwm)
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);
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pwm_beep pwm_beep_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.pwm (pwm),
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.beep (beep)
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);
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endmodule |