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Verilog

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module circuit_arb(
input sys_clk ,
input sys_rst_n ,
input [7: 0] slave_id ,
input [7: 0] opcode ,
input [7: 0] data ,
output [3: 0] led ,
output beep ,
output [7: 0] seg_led ,
output [5: 0] sel_led ,
output dout
);
reg [1: 0] dev_id;
always @(*)begin
case(slave_id)
8'b0011_0000: dev_id = 2'd0;
8'b0011_0001: dev_id = 2'd1;
8'b0011_0010: dev_id = 2'd2;
8'b0011_0011: dev_id = 2'd3;
default: dev_id = 2'd0;
endcase
end
led_circuit led_circuit_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.opcode (opcode[3: 0]),
.data (data[3: 0]),
.dev_id (dev_id),//工作使能00000001
.led (led)
);
beep_circuit beep_circuit_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.dev_id (dev_id),
.opcode (opcode[3: 0]),
.data (data[3: 0]),
.beep (beep)
);
clock_circuit clock_circuit_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.opcode (opcode[3: 0]),
.data (data[3: 0]),
.dev_id (dev_id),//设备地址
.seg_led (seg_led),
.sel_led (sel_led)
);
ws2812_circuit ws2812_circuit_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.opcode (opcode[3: 0]),
.data (data[3: 0]),
.dev_id (dev_id),//设备地址
.dout (dout)
);
endmodule