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42 lines
983 B
Verilog
42 lines
983 B
Verilog
module clock_circuit(
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input sys_clk ,
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input sys_rst_n ,
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input [3: 0] opcode ,
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input [3: 0] data ,
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input [1: 0] dev_id ,//设备地址
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output [7: 0] seg_led ,
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output [5: 0] sel_led
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);
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wire [4: 0] hour;
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wire [5: 0] min ;
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wire [5: 0] sec ;
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timer timer_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.dev_id (dev_id),
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.opcode (opcode),
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.hour (hour),
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.min (min),
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.sec (sec)
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);
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timer_decoder timer_decoder_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.hour (hour),
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.min (min),
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.sec (sec),
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.dev_id (dev_id),
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.opcode (opcode),
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.seg_led (seg_led),
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.sel_led (sel_led)
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);
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// defparam timer_inst.MAX = 5;//5 * 20 = 100ns
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// defparam timer_inst.DAY = 864;//864 * 100 = 86400ns;
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// defparam timer_decoder_inst.FPS = 10;//200ns;
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endmodule
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