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88 lines
2.3 KiB
Verilog
88 lines
2.3 KiB
Verilog
module stark_machine(
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input sys_clk ,
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input sys_rst_n ,
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input rx ,
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output tx ,
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output [3: 0] led ,
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output beep ,
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output [7: 0] seg_led ,
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output [5: 0] sel_led ,
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output dout
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);
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reg [23: 0] instruction_reg;//指令寄存器
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wire [7: 0] opcode;//操作码
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wire [7: 0] slave_id;//电路id
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wire [7: 0] data;//数据
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wire [7: 0] rx_byte;//接受的数据
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wire rx_vld;//串转并有效
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wire [23: 0] instruction;//指令
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reg [1: 0] byte_num;//字节计数器
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wire tx_vld;
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// assign instruction = 24'h01020f;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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instruction_reg <= 24'h000000;
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end
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else if(rx_vld)begin
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instruction_reg <= {instruction_reg[15: 0], rx_byte};
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end
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else begin
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instruction_reg <= instruction_reg;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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byte_num <= 2'd0;
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end
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else if(rx_vld)begin
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byte_num <= byte_num + 1'd1;
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end
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else if(byte_num == 2'd3)begin
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byte_num <= 2'd0;
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end
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else begin
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byte_num <= byte_num;
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end
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end
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assign instruction = (byte_num == 2'd3) ? instruction_reg: 24'h000000;
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//接受上位机
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uart_rx uart_rx_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.rx_din (rx),//数据串行输入
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.rx_dout (rx_byte),//数据并行输出
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.rx_vld (rx_vld)//输出信号有效
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);
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uart_tx uart_tx_inst(
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.tx_din (rx_byte),//并行输入，接受模块传入
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.rx_vld (rx_vld),//接受模块，串转并有效信号
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.tx_vld (tx_vld),
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.tx_dout (tx)//串行输出
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);
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instr_decode instr_decode_inst(
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.instruction (instruction),//指令
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.opcode (opcode),//操作码
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.slave_id (slave_id),//电路id
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.data (data) //数据
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);
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circuit_arb circuit_arb_inst(//仲裁电路
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.sys_clk (sys_clk),
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.sys_rst_n (sys_rst_n),
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.slave_id (slave_id),
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.opcode (opcode),
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.data (data),
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.led (led),
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.beep (beep),
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.seg_led (seg_led),
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.sel_led (sel_led),
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.dout (dout)
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);
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endmodule
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