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107 lines
2.8 KiB
Verilog
107 lines
2.8 KiB
Verilog
`include "param.v"
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module uart_rx(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire rx_din ,//数据串行输入
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output wire [7: 0] rx_dout ,//数据并行输出
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output wire rx_vld //输出信号有效
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);
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parameter BAUD = `SYS_FRQ / `MAX;//获取1bit时钟振动的次数
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reg din_reg0;//同步外来信号，和本时钟域同步
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reg din_reg1;//打拍，获取下降沿
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wire nedge;//下降沿标志
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reg rx_flag;//开始接受标志
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//对bit进行计数寄存器
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reg [3: 0] cnt_bit ;
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wire add_cnt_bit;
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wire end_cnt_bit;
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//对波特率进行计数寄存器
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reg [12: 0] cnt_bps ;
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wire add_cnt_bps ;
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wire end_cnt_bps ;
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//数据寄存器
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reg [7: 0] data_reg;
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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din_reg0 <= 1'b1;
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din_reg1 <= 1'b1;
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end
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else begin
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din_reg0 <= rx_din;
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din_reg1 <= din_reg0;
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end
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end
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assign nedge = ~din_reg0 && din_reg1;//下降沿
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//rx_flag信号约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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rx_flag <= 1'b0;
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end
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else if(nedge)begin//检测到下降沿
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rx_flag <= 1'b1;
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end
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else if(end_cnt_bit)begin//传输完成标志
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rx_flag <= 1'b0;
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end
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else begin
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rx_flag <= rx_flag;//其他时刻保持
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end
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end
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//cnt_bps计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_bps <= 13'd0;
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end
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else if(add_cnt_bps)begin
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if(end_cnt_bps)begin
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cnt_bps <= 13'd0;
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end
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else begin
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cnt_bps <= cnt_bps + 1'd1;
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end
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end
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else begin
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cnt_bps <= cnt_bps;
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end
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end
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assign add_cnt_bps = rx_flag;
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assign end_cnt_bps = add_cnt_bps && cnt_bps == BAUD - 1'd1;
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//cnt_bit计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_bit <= 4'd0;
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end
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else if(add_cnt_bit)begin
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if(end_cnt_bit)begin
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cnt_bit <= 4'd0;
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end
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else begin
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cnt_bit <= cnt_bit + 1'd1;
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end
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end
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else begin
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cnt_bit <= cnt_bit;
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end
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end
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assign add_cnt_bit = end_cnt_bps;//比特计数开始条件
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assign end_cnt_bit = add_cnt_bit && cnt_bit == 4'd8;//0-8
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//对data_reg进行约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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data_reg <= 8'hx;
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end
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else if((cnt_bit >= 4'd1 && cnt_bit <= 4'd8) && (cnt_bps == BAUD >> 1))begin
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data_reg[cnt_bit - 1'd1] = din_reg0;//对输入数据进行采样
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end
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else begin
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data_reg <= data_reg;
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end
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end
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assign rx_dout = data_reg;//数据输出
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assign rx_vld = end_cnt_bit;//串转并结束标志
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endmodule
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