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991 B
Verilog

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module ws2812_circuit(
input sys_clk ,
input sys_rst_n ,
input [3: 0] opcode ,
input [3: 0] data ,
input [1: 0] dev_id ,//设备地址
output dout
);
wire [4: 0] bit_num;
wire [6: 0] led_num;
wire [1: 0] frame ;
wire bit ;
ws2812_ctrl ws2812_ctrl_inst(
.sys_clk (sys_clk) ,//系统时钟50MHz
.sys_rst_n (sys_rst_n) ,//系统复位,下降沿有效
.bit (bit) ,//data_cfg给的bit
.opcode (opcode) ,
.data (data) ,
.dev_id (dev_id) ,//设备地址
.frame (frame) ,
.bit_num (bit_num) ,//bit计数寄存器
.led_num (led_num) ,//led计数寄存器
.dout (dout) //点阵输出
);
data_cfg data_cfg_inst(
.bit_num (bit_num),
.led_num (led_num),
.frame (frame) ,
.bit (bit)
);
endmodule