breath_led/rtl/breath_led.v

//新的计数器设计
module breath_led(
    input   wire         sys_clk     ,
    input   wire         sys_rst_n   ,

    output  wire  [3: 0] led 
);
parameter MAX_1US = 6'd50,
          MAX_1MS = 10'd1000,
          MAX_1S  = 10'd1000;
reg [5: 0] cnt_us;
wire       add_cnt_us;
wire       end_cnt_us;

reg [9: 0] cnt_ms;
wire       add_cnt_ms;
wire       end_cnt_ms;

reg [9: 0] cnt_s;
wire       add_cnt_s;
wire       end_cnt_s;

reg        flag;
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt_us <= 6'd0;
    end 
    else if(add_cnt_us)begin
        if(end_cnt_us)begin
            cnt_us <= 6'd0;            
        end 
        else begin
            cnt_us <= cnt_us + 1'd1;
        end 
    end 
    else begin
        cnt_us <= cnt_us;
    end 
end
assign add_cnt_us = 1'b1;
assign end_cnt_us = add_cnt_us && cnt_us == MAX_1US - 1'd1;

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_ms <= 10'd0;
    end 
    else if(add_cnt_ms)begin
        if(end_cnt_ms)begin
            cnt_ms <= 10'd0;
        end 
        else begin
            cnt_ms <= cnt_ms + 1'd1;
        end 
    end 
    else begin
        cnt_ms <= cnt_ms;
    end 
end 
assign add_cnt_ms = end_cnt_us;
assign end_cnt_ms = add_cnt_ms && cnt_ms == MAX_1MS - 1'd1;

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_s <= 10'd0;
    end 
    else if(add_cnt_s)begin
        if(end_cnt_s)begin
            cnt_s <= 10'd0;
        end 
        else begin
            cnt_s <= cnt_s + 1'd1;
        end 
    end 
    else begin
        cnt_s <= cnt_s;
    end 
end 
assign add_cnt_s = end_cnt_ms;
assign end_cnt_s = add_cnt_s && cnt_s == MAX_1S - 1'd1;

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag <= 1'b0;
    end 
    else if(end_cnt_s)begin
        flag <= ~flag;
    end 
    else begin
        flag <= flag;
    end 
end 
assign led = (flag == 1'b0) ? {4{cnt_ms > cnt_s}}: {4{cnt_ms < cnt_s}};

endmodule