From ca406b8d59b5518c8603c8166d957224c92e449f Mon Sep 17 00:00:00 2001 From: lincaigui <18166451309@163.com> Date: Tue, 23 Apr 2024 12:45:48 +0800 Subject: [PATCH] finish --- readme.md | 1 + rtl/breath_led.v | 94 ++++++++++++++++++++++++++++++++++++++ tcl/C4_pin.tcl | 114 +++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 209 insertions(+) create mode 100644 readme.md create mode 100644 rtl/breath_led.v create mode 100644 tcl/C4_pin.tcl diff --git a/readme.md b/readme.md new file mode 100644 index 0000000..c436e3d --- /dev/null +++ b/readme.md @@ -0,0 +1 @@ +## FPGA 呼吸灯 \ No newline at end of file diff --git a/rtl/breath_led.v b/rtl/breath_led.v new file mode 100644 index 0000000..1488c47 --- /dev/null +++ b/rtl/breath_led.v @@ -0,0 +1,94 @@ +//新的计数器设计 +module breath_led( + input wire sys_clk , + input wire sys_rst_n , + + output wire [3: 0] led +); +parameter MAX_1US = 6'd50, + MAX_1MS = 10'd1000, + MAX_1S = 10'd1000; +reg [5: 0] cnt_us; +wire add_cnt_us; +wire end_cnt_us; + +reg [9: 0] cnt_ms; +wire add_cnt_ms; +wire end_cnt_ms; + +reg [9: 0] cnt_s; +wire add_cnt_s; +wire end_cnt_s; + +reg flag; +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + cnt_us <= 6'd0; + end + else if(add_cnt_us)begin + if(end_cnt_us)begin + cnt_us <= 6'd0; + end + else begin + cnt_us <= cnt_us + 1'd1; + end + end + else begin + cnt_us <= cnt_us; + end +end +assign add_cnt_us = 1'b1; +assign end_cnt_us = add_cnt_us && cnt_us == MAX_1US - 1'd1; + +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cnt_ms <= 10'd0; + end + else if(add_cnt_ms)begin + if(end_cnt_ms)begin + cnt_ms <= 10'd0; + end + else begin + cnt_ms <= cnt_ms + 1'd1; + end + end + else begin + cnt_ms <= cnt_ms; + end +end +assign add_cnt_ms = end_cnt_us; +assign end_cnt_ms = add_cnt_ms && cnt_ms == MAX_1MS - 1'd1; + +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cnt_s <= 10'd0; + end + else if(add_cnt_s)begin + if(end_cnt_s)begin + cnt_s <= 10'd0; + end + else begin + cnt_s <= cnt_s + 1'd1; + end + end + else begin + cnt_s <= cnt_s; + end +end +assign add_cnt_s = end_cnt_ms; +assign end_cnt_s = add_cnt_s && cnt_s == MAX_1S - 1'd1; + +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + flag <= 1'b0; + end + else if(end_cnt_s)begin + flag <= ~flag; + end + else begin + flag <= flag; + end +end +assign led = (flag == 1'b0) ? {4{cnt_ms > cnt_s}}: {4{cnt_ms < cnt_s}}; + +endmodule \ No newline at end of file diff --git a/tcl/C4_pin.tcl b/tcl/C4_pin.tcl new file mode 100644 index 0000000..dfbe2a9 --- /dev/null +++ b/tcl/C4_pin.tcl @@ -0,0 +1,114 @@ +#引脚参数导入脚本 +#时钟、复位 +set_location_assignment PIN_E1 -to sys_clk +set_location_assignment PIN_E15 -to sys_rst_n + +#UART +#set_location_assignment PIN_M2 -to uart_rx +#set_location_assignment PIN_G1 -to uart_tx + +#LED +set_location_assignment PIN_D16 -to led[3] +set_location_assignment PIN_F15 -to led[2] +set_location_assignment PIN_F16 -to led[1] +set_location_assignment PIN_G15 -to led[0] + +#独立按键 +# set_location_assignment PIN_M15 -to key_in[2] +# set_location_assignment PIN_M16 -to key_in[1] +# set_location_assignment PIN_E16 -to key_in + +#数码管选段 +# set_location_assignment PIN_B7 -to seg_led[0] +# set_location_assignment PIN_A8 -to seg_led[1] +# set_location_assignment PIN_A6 -to seg_led[2] +# set_location_assignment PIN_B5 -to seg_led[3] +# set_location_assignment PIN_B6 -to seg_led[4] +# set_location_assignment PIN_A7 -to seg_led[5] +# set_location_assignment PIN_B8 -to seg_led[6] +# set_location_assignment PIN_A5 -to seg_led[7] + +#数码管片选w· +# set_location_assignment PIN_A4 -to sel_led[0] +# set_location_assignment PIN_B4 -to sel_led[1] +# set_location_assignment PIN_A3 -to sel_led[2] +# set_location_assignment PIN_B3 -to sel_led[3] +# set_location_assignment PIN_A2 -to sel_led[4] +# set_location_assignment PIN_B1 -to sel_led[5] + +#ds18b20 +# set_location_assignment PIN_E6 -to dq + +#蜂鸣器 +#set_location_assignment PIN_J1 -to buzzer + +#SDRAM + #地址 +#set_location_assignment PIN_T8 -to addr[0] +#set_location_assignment PIN_P9 -to addr[1] +#set_location_assignment PIN_T9 -to addr[2] +#set_location_assignment PIN_R9 -to addr[3] +#set_location_assignment PIN_L16 -to addr[4] +#set_location_assignment PIN_L15 -to addr[5] +#set_location_assignment PIN_N16 -to addr[6] +#set_location_assignment PIN_N15 -to addr[7] +#set_location_assignment PIN_P16 -to addr[8] +#set_location_assignment PIN_P15 -to addr[9] +#set_location_assignment PIN_R8 -to addr[10] +#set_location_assignment PIN_R16 -to addr[11] +#set_location_assignment PIN_T15 -to addr[12] + + #数据 +#set_location_assignment PIN_R5 -to dq[0] +#set_location_assignment PIN_T4 -to dq[1] +#set_location_assignment PIN_T3 -to dq[2] +#set_location_assignment PIN_R3 -to dq[3] +#set_location_assignment PIN_T2 -to dq[4] +#set_location_assignment PIN_R1 -to dq[5] +#set_location_assignment PIN_P2 -to dq[6] +#set_location_assignment PIN_P1 -to dq[7] +#set_location_assignment PIN_R13 -to dq[8] +#set_location_assignment PIN_T13 -to dq[9] +#set_location_assignment PIN_R12 -to dq[10] +#set_location_assignment PIN_T12 -to dq[11] +#set_location_assignment PIN_T10 -to dq[12] +#set_location_assignment PIN_R10 -to dq[13] +#set_location_assignment PIN_T11 -to dq[14] +#set_location_assignment PIN_R11 -to dq[15] + + #bank +#set_location_assignment PIN_R7 -to bank[0] +#set_location_assignment PIN_T7 -to bank[1] + + #dqm +#set_location_assignment PIN_N2 -to dqm[0] +#set_location_assignment PIN_T14 -to dqm[1] + + #时钟 +#set_location_assignment PIN_R4 -to sdram_clk + + #控制信号 +#set_location_assignment PIN_R14 -to cke +#set_location_assignment PIN_T6 -to cs_n +#set_location_assignment PIN_R6 -to ras_n +#set_location_assignment PIN_T5 -to cas_n +#set_location_assignment PIN_N1 -to we_n + + +#flash +#set_location_assignment PIN_H2 -to miso +#set_location_assignment PIN_C1 -to mosi +#set_location_assignment PIN_H1 -to sclk +#set_location_assignment PIN_D2 -to cs_n + +#EEPROM +#set_location_assignment PIN_L2 -to sda +#set_location_assignment PIN_L1 -to sclk + +#VGA + +#摄像头 + + + +