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94 lines
2.0 KiB
Verilog
94 lines
2.0 KiB
Verilog
//新的计数器设计
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module breath_led(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire [3: 0] led
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);
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parameter MAX_1US = 6'd50,
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MAX_1MS = 10'd1000,
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MAX_1S = 10'd1000;
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reg [5: 0] cnt_us;
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wire add_cnt_us;
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wire end_cnt_us;
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reg [9: 0] cnt_ms;
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wire add_cnt_ms;
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wire end_cnt_ms;
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reg [9: 0] cnt_s;
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wire add_cnt_s;
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wire end_cnt_s;
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reg flag;
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_us <= 6'd0;
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end
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else if(add_cnt_us)begin
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if(end_cnt_us)begin
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cnt_us <= 6'd0;
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end
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else begin
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cnt_us <= cnt_us + 1'd1;
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end
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end
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else begin
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cnt_us <= cnt_us;
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end
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end
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assign add_cnt_us = 1'b1;
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assign end_cnt_us = add_cnt_us && cnt_us == MAX_1US - 1'd1;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_ms <= 10'd0;
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end
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else if(add_cnt_ms)begin
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if(end_cnt_ms)begin
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cnt_ms <= 10'd0;
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end
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else begin
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cnt_ms <= cnt_ms + 1'd1;
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end
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end
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else begin
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cnt_ms <= cnt_ms;
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end
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end
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assign add_cnt_ms = end_cnt_us;
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assign end_cnt_ms = add_cnt_ms && cnt_ms == MAX_1MS - 1'd1;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_s <= 10'd0;
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end
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else if(add_cnt_s)begin
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if(end_cnt_s)begin
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cnt_s <= 10'd0;
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end
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else begin
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cnt_s <= cnt_s + 1'd1;
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end
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end
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else begin
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cnt_s <= cnt_s;
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end
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end
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assign add_cnt_s = end_cnt_ms;
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assign end_cnt_s = add_cnt_s && cnt_s == MAX_1S - 1'd1;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag <= 1'b0;
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end
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else if(end_cnt_s)begin
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flag <= ~flag;
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end
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else begin
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flag <= flag;
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end
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end
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assign led = (flag == 1'b0) ? {4{cnt_ms > cnt_s}}: {4{cnt_ms < cnt_s}};
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endmodule |