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25 lines
537 B
Coq
25 lines
537 B
Coq
7 months ago
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`timescale 1ns/1ns
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module clock_tb();
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parameter CYCLE=20;
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reg sys_clk ;
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reg sys_rst_n ;
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wire [7: 0] seg_led ;
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wire [5: 0] sel_led ;
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always #(CYCLE / 2) sys_clk = ~sys_clk;
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initial begin
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sys_clk = 1'b0 ;
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sys_rst_n = 1'b0 ;
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#(CYCLE) ;
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sys_rst_n = 1'b1 ;
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#(CYCLE * 5 * 864);//86400ns
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$stop ;
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end
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clock_top clock_top_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n),
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.seg_led (seg_led ),
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.sel_led (sel_led )
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);
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endmodule
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