digital_clock/rtl/timer_decoder.v

module timer_decoder(
    input   wire             sys_clk    ,
    input   wire             sys_rst_n  ,
    input   wire    [4: 0]   hour       ,
    input   wire    [5: 0]   min        ,
    input   wire    [5: 0]   sec        ,

    output  reg     [7: 0]   seg_led    ,
    output  reg     [5: 0]   sel_led
);
parameter FPS = 10'd1000;//20us
reg [9: 0] cnt_fps;
reg [3: 0] value  ;
//20us计数器设计
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_fps <= 10'd0;
    end     
    else if(cnt_fps == FPS - 1'd1)begin
        cnt_fps <= 10'd0;
    end 
    else begin
        cnt_fps <= cnt_fps + 1'd1;
    end 
end 
//sel_led信号进行约束
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        sel_led <= 6'b111_110;
    end 
    else if(cnt_fps == FPS - 1'd1)begin
        sel_led <= {sel_led[4: 0], sel_led[5]};//进行位拼接
    end 
    else begin
        sel_led <= sel_led;//数据保持
    end
end 

always @(*)begin
    case(sel_led)
        6'b111_110: value = hour / 10;
        6'b111_101: value = hour % 10;
        6'b111_011: value = min / 10 ;
        6'b110_111: value = min % 10 ;
        6'b101_111: value = sec / 10 ;
        6'b011_111: value = sec % 10 ;
        default   : value = 0        ; 
    endcase
end 

always @(*)begin
    case(value)
        4'd0    :   seg_led = 8'b1100_0000;   
        4'd1    :   seg_led = 8'b1111_1001;   
        4'd2    :   seg_led = 8'b1010_0100;   
        4'd3    :   seg_led = 8'b1011_0000;   
        4'd4    :   seg_led = 8'b1001_1001;   
        4'd5    :   seg_led = 8'b1001_0010;   
        4'd6    :   seg_led = 8'b1000_0010;   
        4'd7    :   seg_led = 8'b1111_1000;   
        4'd8    :   seg_led = 8'b1000_0000;   
        4'd9    :   seg_led = 8'b1001_0000;   
        default :   seg_led = 8'b1100_0000;   
    endcase
end 
endmodule