`timescale 1ns/1ns
module clock_tb();
parameter CYCLE=20;

reg         sys_clk     ;
reg         sys_rst_n   ;
wire [7: 0] seg_led     ;
wire [5: 0] sel_led     ;
always #(CYCLE / 2) sys_clk = ~sys_clk;
initial begin
    sys_clk   = 1'b0  ;
    sys_rst_n = 1'b0  ;
    #(CYCLE)          ;
    sys_rst_n = 1'b1  ;
    #(CYCLE * 5 * 864);//86400ns
    $stop             ;
end
clock_top   clock_top_inst(
.sys_clk        (sys_clk  ),
.sys_rst_n      (sys_rst_n),
       
.seg_led        (seg_led  ),
.sel_led        (sel_led  )
);
endmodule