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43 lines
1.1 KiB
Verilog
43 lines
1.1 KiB
Verilog
module timer(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire [4: 0] hour ,
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output wire [5: 0] min ,
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output wire [5: 0] sec
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);
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parameter MAX = 28'd50_000_000;
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parameter DAY = 17'd86400;
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reg [27: 0] cnt_s;//秒计数寄存器
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reg [16: 0] cnt_day;//一天多少秒计数寄存器
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//秒计数器设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_s <= 28'd0;
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end
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else if(cnt_s == MAX - 1'd1)begin
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cnt_s <= 28'd0;
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end
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else begin
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cnt_s <= cnt_s + 1'd1;
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end
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end
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//天计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_day <= 17'd0;
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end
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else if((cnt_day == DAY - 1'd1) && (cnt_s == MAX - 1'd1))begin
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cnt_day <= 17'd0;
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end
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else if(cnt_s == MAX - 1'd1)begin
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cnt_day <= cnt_day + 1'd1;
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end
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else begin
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cnt_day <= cnt_day;
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end
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end
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assign hour = cnt_day / 3600;//解析小时
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assign min = cnt_day % 3600 / 60;//解析分钟
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assign sec = cnt_day % 60;//解析秒
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endmodule
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