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66 lines
1.9 KiB
Verilog
66 lines
1.9 KiB
Verilog
module timer_decoder(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire [4: 0] hour ,
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input wire [5: 0] min ,
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input wire [5: 0] sec ,
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output reg [7: 0] seg_led ,
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output reg [5: 0] sel_led
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);
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parameter FPS = 10'd1000;//20us
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reg [9: 0] cnt_fps;
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reg [3: 0] value ;
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//20us计数器设计
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_fps <= 10'd0;
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end
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else if(cnt_fps == FPS - 1'd1)begin
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cnt_fps <= 10'd0;
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end
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else begin
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cnt_fps <= cnt_fps + 1'd1;
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end
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end
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//sel_led信号进行约束
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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sel_led <= 6'b111_110;
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end
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else if(cnt_fps == FPS - 1'd1)begin
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sel_led <= {sel_led[4: 0], sel_led[5]};//进行位拼接
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end
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else begin
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sel_led <= sel_led;//数据保持
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end
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end
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always @(*)begin
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case(sel_led)
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6'b111_110: value = hour / 10;
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6'b111_101: value = hour % 10;
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6'b111_011: value = min / 10 ;
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6'b110_111: value = min % 10 ;
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6'b101_111: value = sec / 10 ;
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6'b011_111: value = sec % 10 ;
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default : value = 0 ;
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endcase
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end
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always @(*)begin
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case(value)
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4'd0 : seg_led = 8'b1100_0000;
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4'd1 : seg_led = 8'b1111_1001;
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4'd2 : seg_led = 8'b1010_0100;
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4'd3 : seg_led = 8'b1011_0000;
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4'd4 : seg_led = 8'b1001_1001;
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4'd5 : seg_led = 8'b1001_0010;
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4'd6 : seg_led = 8'b1000_0010;
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4'd7 : seg_led = 8'b1111_1000;
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4'd8 : seg_led = 8'b1000_0000;
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4'd9 : seg_led = 8'b1001_0000;
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default : seg_led = 8'b1100_0000;
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endcase
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end
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endmodule
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