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61 lines
1.2 KiB
Coq
61 lines
1.2 KiB
Coq
7 months ago
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module divider_five1(
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input wire sys_clk,
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input wire sys_rst_n,
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output reg led
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);
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parameter MAX = 24'd10_000_000;
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reg [23: 0] cnt_clk;
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reg [2: 0] cnt;
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reg clk_flag;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt <= 3'd0;
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end
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else if(cnt == 3'd4)begin
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cnt <= 3'd0;
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end
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else begin
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cnt <= cnt + 1'd1;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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clk_flag <= 1'b0;
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end
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else if(cnt == 3'd3)begin
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clk_flag <= 1'b1;
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end
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else begin
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clk_flag <= 1'b0;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_clk <= 24'd0;
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end
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else if(cnt_clk == MAX - 1'd1)begin
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cnt_clk <= 24'd0;
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end
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else if(clk_flag)begin
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cnt_clk <= cnt_clk + 1'd1;
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end
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else begin
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cnt_clk <= cnt_clk;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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led <= 1'b0;
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end
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else if(cnt_clk == MAX - 1'd1)begin
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led <= ~led;
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end
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else begin
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led <= led;
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end
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end
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endmodule
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