divider/rtl/divider_six0.v

//这种分频没有直接使用全局时钟树
//低速系统没有问题，高速系统不稳定
module divider_six0(
    input   wire   sys_clk,
    input   wire   sys_rst_n,

    output  reg    led
);
parameter MAX = 23'd8_333_333;
reg [1: 0]  cnt;
reg         clk_out;
reg [22: 0] cnt_out;
always @(posedge sys_clk or negedge sys_rst_n) begin
    if(!sys_rst_n)begin
        cnt <= 2'd0;
    end 
    else if(cnt == 2'd2)begin
        cnt <= 2'd0;
    end 
    else begin
        cnt <= cnt + 1'd1;
    end 
end
//clk_out:6 分频 50%占空比输出
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        clk_out <= 1'b0;
    end 
    else if(cnt == 2'd2)begin
        clk_out <= ~clk_out;
    end 
    else begin
        clk_out <= clk_out;
    end 
end 

always @(posedge clk_out or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_out <= 23'd0;
    end 
    else if(cnt_out == MAX - 1'd1)begin
        cnt_out <= 23'd0;
    end 
    else begin
        cnt_out <= cnt_out + 1'd1;
    end 
end 
//使用分频时钟控制led，时钟120ns周期，频率是10^9/120 = 8,333,333
always @(posedge clk_out or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        led <= led;
    end 
    else if(cnt_out == MAX - 1'd1)begin
        led <= ~led;
    end  
    else begin
        led <= led;
    end    
end 
endmodule