commit 971bfcfea27d4baccba9dfa5e4aa861d8da3d843
Author: lincaigui <18166451309@163.com>
Date:   Tue Apr 23 13:16:46 2024 +0800

    finish

diff --git a/readme.md b/readme.md
new file mode 100644
index 0000000..f4838dd
--- /dev/null
+++ b/readme.md
@@ -0,0 +1,3 @@
+## FPGA时钟分频
+### 1.FPGA计数分频
+### 2.FPGA偶数分频
\ No newline at end of file
diff --git a/rtl/divider_five0.v b/rtl/divider_five0.v
new file mode 100644
index 0000000..c4159ff
--- /dev/null
+++ b/rtl/divider_five0.v
@@ -0,0 +1,80 @@
+module divider_five0(
+    input  wire  sys_clk,
+    input  wire  sys_rst_n,
+
+    output reg   led
+);
+parameter MAX = 24'd10_000_000;
+reg [2: 0]  cnt     ;
+reg         clk1    ;
+reg         clk2    ;
+wire        clk     ;
+reg [23: 0] cnt_clk ;
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt <= 3'd0;
+    end 
+    else if(cnt == 3'd4)begin
+        cnt <= 3'd0;
+    end 
+    else begin
+        cnt <= cnt + 1'd1;
+    end 
+end 
+
+//clk1根据上升沿改变
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        clk1 <= 1'b1;
+    end 
+    else if(cnt == 3'd2)begin
+        clk1 <= 1'b0;
+    end 
+    else if(cnt == 3'd4)begin
+        clk1 <= 1'b1;
+    end 
+    else begin
+        clk1 <= clk1;
+    end 
+end 
+//clk2根据下降沿改变
+always @(negedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        clk2 <= 1'b1;
+    end 
+    else if(cnt == 3'd2)begin
+        clk2 <= 1'b0;
+    end 
+    else if(cnt == 3'd4)begin
+        clk2 <= 1'b1;
+    end 
+    else begin
+        clk2 <= clk2;
+    end 
+end 
+assign clk = clk1 & clk2;
+//时钟频率，10^9 / 100 = 10_000_000;
+always @(posedge clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)begin
+        cnt_clk <= 24'd0;
+    end 
+    else if(cnt_clk == MAX - 1'd1)begin
+        cnt_clk <= 24'd0;
+    end 
+    else begin
+        cnt_clk <= cnt_clk + 1'd1;
+    end 
+end
+
+always @(posedge clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        led <= 1'b0;
+    end 
+    else if(cnt_clk == MAX - 1'd1)begin
+        led <= ~led;
+    end 
+    else begin
+        led <= led;
+    end 
+end 
+endmodule
\ No newline at end of file
diff --git a/rtl/divider_five1.v b/rtl/divider_five1.v
new file mode 100644
index 0000000..1519409
--- /dev/null
+++ b/rtl/divider_five1.v
@@ -0,0 +1,61 @@
+module divider_five1(
+    input  wire  sys_clk,
+    input  wire  sys_rst_n,
+
+    output reg   led
+);
+parameter MAX = 24'd10_000_000;
+reg [23: 0] cnt_clk;
+reg [2: 0]  cnt;
+reg         clk_flag;
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt <= 3'd0;
+    end 
+    else if(cnt == 3'd4)begin
+        cnt <= 3'd0;
+    end 
+    else begin
+        cnt <= cnt + 1'd1;
+    end 
+end 
+
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        clk_flag <= 1'b0;
+    end 
+    else if(cnt == 3'd3)begin
+        clk_flag <= 1'b1;
+    end 
+    else begin
+        clk_flag <= 1'b0;
+    end 
+end 
+
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_clk <= 24'd0;
+    end 
+    else if(cnt_clk == MAX - 1'd1)begin
+        cnt_clk <= 24'd0;
+    end 
+    else if(clk_flag)begin
+        cnt_clk <= cnt_clk + 1'd1;
+    end 
+    else begin
+        cnt_clk <= cnt_clk;
+    end 
+end 
+
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        led <= 1'b0;
+    end 
+    else if(cnt_clk == MAX - 1'd1)begin
+        led <= ~led;
+    end 
+    else begin
+        led <= led;
+    end 
+end 
+endmodule 
\ No newline at end of file
diff --git a/rtl/divider_six0.v b/rtl/divider_six0.v
new file mode 100644
index 0000000..08446e9
--- /dev/null
+++ b/rtl/divider_six0.v
@@ -0,0 +1,60 @@
+//这种分频没有直接使用全局时钟树
+//低速系统没有问题，高速系统不稳定
+module divider_six0(
+    input   wire   sys_clk,
+    input   wire   sys_rst_n,
+
+    output  reg    led
+);
+parameter MAX = 23'd8_333_333;
+reg [1: 0]  cnt;
+reg         clk_out;
+reg [22: 0] cnt_out;
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)begin
+        cnt <= 2'd0;
+    end 
+    else if(cnt == 2'd2)begin
+        cnt <= 2'd0;
+    end 
+    else begin
+        cnt <= cnt + 1'd1;
+    end 
+end
+//clk_out:6 分频 50%占空比输出
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        clk_out <= 1'b0;
+    end 
+    else if(cnt == 2'd2)begin
+        clk_out <= ~clk_out;
+    end 
+    else begin
+        clk_out <= clk_out;
+    end 
+end 
+
+always @(posedge clk_out or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_out <= 23'd0;
+    end 
+    else if(cnt_out == MAX - 1'd1)begin
+        cnt_out <= 23'd0;
+    end 
+    else begin
+        cnt_out <= cnt_out + 1'd1;
+    end 
+end 
+//使用分频时钟控制led，时钟120ns周期，频率是10^9/120 = 8,333,333
+always @(posedge clk_out or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        led <= led;
+    end 
+    else if(cnt_out == MAX - 1'd1)begin
+        led <= ~led;
+    end  
+    else begin
+        led <= led;
+    end    
+end 
+endmodule
\ No newline at end of file
diff --git a/rtl/divider_six1.v b/rtl/divider_six1.v
new file mode 100644
index 0000000..baa6614
--- /dev/null
+++ b/rtl/divider_six1.v
@@ -0,0 +1,61 @@
+//这个分频里面全是使用全局时钟树，无论高速还是低速系统都更稳定
+module divider_six1(
+    input  wire  sys_clk,
+    input  wire  sys_rst_n,
+
+    output reg   led
+);
+parameter MAX = 23'd8_333_333;
+reg [2: 0]  cnt;
+reg         flag;
+reg [22: 0] cnt_flag;
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt <= 3'd0;
+    end 
+    else if(cnt == 3'd5)begin
+        cnt <= 3'd0;
+    end 
+    else begin
+        cnt <= cnt + 1'd1;
+    end 
+end 
+//使用flag计数0~5，时钟保持全局时钟
+always @(posedge sys_clk or negedge sys_rst_n) begin
+    if(!sys_rst_n)begin
+        flag <= 1'b0;
+    end 
+    else if(cnt == 3'd5)begin
+        flag <= 1'b1;
+    end 
+    else begin
+        flag <= 1'b0;
+    end 
+end
+//根据脉冲信号加1
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        cnt_flag <= 23'd0;
+    end 
+    else if(cnt_flag == MAX - 1'd1)begin
+        cnt_flag <= 23'd0;
+    end 
+    else if(flag)begin
+        cnt_flag <= cnt_flag + 1'd1;
+    end 
+    else begin
+        cnt_flag <= cnt_flag;
+    end 
+end 
+always @(posedge sys_clk or negedge sys_rst_n)begin
+    if(!sys_rst_n)begin
+        led <= 1'b0;
+    end 
+    else if(cnt_flag == MAX - 1'd1)begin
+        led <= ~led;
+    end 
+    else begin
+        led <= led;
+    end 
+end 
+endmodule
\ No newline at end of file
diff --git a/tcl/C4_pin.tcl b/tcl/C4_pin.tcl
new file mode 100644
index 0000000..dac61fc
--- /dev/null
+++ b/tcl/C4_pin.tcl
@@ -0,0 +1,114 @@
+#引脚参数导入脚本
+#时钟、复位
+set_location_assignment PIN_E1 -to sys_clk
+set_location_assignment PIN_E15 -to sys_rst_n
+
+#UART
+#set_location_assignment PIN_M2 -to uart_rx
+#set_location_assignment PIN_G1 -to uart_tx
+
+#LED
+#set_location_assignment PIN_D16 -to led[3]
+#set_location_assignment PIN_F15 -to led[2]
+#set_location_assignment PIN_F16 -to led[1]
+set_location_assignment PIN_G15 -to led
+
+#独立按键
+# set_location_assignment PIN_M15 -to key_in[2]
+# set_location_assignment PIN_M16 -to key_in[1]
+# set_location_assignment PIN_E16 -to key_in[0]
+
+#数码管选段
+# set_location_assignment PIN_B7 -to seg_led[0]
+# set_location_assignment PIN_A8 -to seg_led[1]
+# set_location_assignment PIN_A6 -to seg_led[2]
+# set_location_assignment PIN_B5 -to seg_led[3]
+# set_location_assignment PIN_B6 -to seg_led[4]
+# set_location_assignment PIN_A7 -to seg_led[5]
+# set_location_assignment PIN_B8 -to seg_led[6]
+# set_location_assignment PIN_A5 -to seg_led[7]
+
+#数码管片选w·
+# set_location_assignment PIN_A4 -to sel_led[0]
+# set_location_assignment PIN_B4 -to sel_led[1]
+# set_location_assignment PIN_A3 -to sel_led[2]
+# set_location_assignment PIN_B3 -to sel_led[3]
+# set_location_assignment PIN_A2 -to sel_led[4]
+# set_location_assignment PIN_B1 -to sel_led[5]
+
+#ds18b20
+# set_location_assignment PIN_E6 -to dq
+
+#蜂鸣器
+#set_location_assignment PIN_J1 -to buzzer
+
+#SDRAM
+    #地址
+#set_location_assignment PIN_T8    -to addr[0]  
+#set_location_assignment PIN_P9    -to addr[1]
+#set_location_assignment PIN_T9    -to addr[2]
+#set_location_assignment PIN_R9    -to addr[3]
+#set_location_assignment PIN_L16   -to addr[4]
+#set_location_assignment PIN_L15   -to addr[5]
+#set_location_assignment PIN_N16   -to addr[6]
+#set_location_assignment PIN_N15   -to addr[7]
+#set_location_assignment PIN_P16   -to addr[8]
+#set_location_assignment PIN_P15   -to addr[9]
+#set_location_assignment PIN_R8    -to addr[10]
+#set_location_assignment PIN_R16   -to addr[11]
+#set_location_assignment PIN_T15   -to addr[12]
+    
+    #数据
+#set_location_assignment PIN_R5    -to dq[0]
+#set_location_assignment PIN_T4    -to dq[1]
+#set_location_assignment PIN_T3    -to dq[2]
+#set_location_assignment PIN_R3    -to dq[3]
+#set_location_assignment PIN_T2    -to dq[4]
+#set_location_assignment PIN_R1    -to dq[5]
+#set_location_assignment PIN_P2    -to dq[6]
+#set_location_assignment PIN_P1    -to dq[7]
+#set_location_assignment PIN_R13   -to dq[8]
+#set_location_assignment PIN_T13   -to dq[9]
+#set_location_assignment PIN_R12   -to dq[10]
+#set_location_assignment PIN_T12   -to dq[11]
+#set_location_assignment PIN_T10   -to dq[12]
+#set_location_assignment PIN_R10   -to dq[13]
+#set_location_assignment PIN_T11   -to dq[14]
+#set_location_assignment PIN_R11   -to dq[15]
+
+    #bank
+#set_location_assignment PIN_R7   -to bank[0]
+#set_location_assignment PIN_T7   -to bank[1]
+
+    #dqm
+#set_location_assignment PIN_N2    -to dqm[0]
+#set_location_assignment PIN_T14   -to dqm[1]
+    
+    #时钟
+#set_location_assignment PIN_R4    -to sdram_clk
+
+    #控制信号
+#set_location_assignment PIN_R14   -to cke
+#set_location_assignment PIN_T6    -to cs_n
+#set_location_assignment PIN_R6    -to ras_n
+#set_location_assignment PIN_T5    -to cas_n
+#set_location_assignment PIN_N1    -to we_n
+
+
+#flash
+#set_location_assignment PIN_H2    -to miso   
+#set_location_assignment PIN_C1    -to mosi
+#set_location_assignment PIN_H1    -to sclk
+#set_location_assignment PIN_D2    -to cs_n
+
+#EEPROM 
+#set_location_assignment PIN_L2 -to sda
+#set_location_assignment PIN_L1 -to sclk
+
+#VGA
+
+#摄像头
+
+
+
+