module divider_five1(
    input  wire  sys_clk,
    input  wire  sys_rst_n,

    output reg   led
);
parameter MAX = 24'd10_000_000;
reg [23: 0] cnt_clk;
reg [2: 0]  cnt;
reg         clk_flag;
always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt <= 3'd0;
    end 
    else if(cnt == 3'd4)begin
        cnt <= 3'd0;
    end 
    else begin
        cnt <= cnt + 1'd1;
    end 
end 

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        clk_flag <= 1'b0;
    end 
    else if(cnt == 3'd3)begin
        clk_flag <= 1'b1;
    end 
    else begin
        clk_flag <= 1'b0;
    end 
end 

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        cnt_clk <= 24'd0;
    end 
    else if(cnt_clk == MAX - 1'd1)begin
        cnt_clk <= 24'd0;
    end 
    else if(clk_flag)begin
        cnt_clk <= cnt_clk + 1'd1;
    end 
    else begin
        cnt_clk <= cnt_clk;
    end 
end 

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        led <= 1'b0;
    end 
    else if(cnt_clk == MAX - 1'd1)begin
        led <= ~led;
    end 
    else begin
        led <= led;
    end 
end 
endmodule