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module divider_five0 (
input wire sys_clk ,
input wire sys_rst_n ,
output reg led
) ;
parameter MAX = 24 'd10 _000_000 ;
reg [ 2 : 0 ] cnt ;
reg clk1 ;
reg clk2 ;
wire clk ;
reg [ 23 : 0 ] cnt_clk ;
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
cnt < = 3 'd0 ;
end
else if ( cnt = = 3 'd4 ) begin
cnt < = 3 'd0 ;
end
else begin
cnt < = cnt + 1 'd1 ;
end
end
//clk1根据上升沿改变
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
clk1 < = 1 'b1 ;
end
else if ( cnt = = 3 'd2 ) begin
clk1 < = 1 'b0 ;
end
else if ( cnt = = 3 'd4 ) begin
clk1 < = 1 'b1 ;
end
else begin
clk1 < = clk1 ;
end
end
//clk2根据下降沿改变
always @ ( negedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
clk2 < = 1 'b1 ;
end
else if ( cnt = = 3 'd2 ) begin
clk2 < = 1 'b0 ;
end
else if ( cnt = = 3 'd4 ) begin
clk2 < = 1 'b1 ;
end
else begin
clk2 < = clk2 ;
end
end
assign clk = clk1 & clk2 ;
//时钟频率，
always @ ( posedge clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
cnt_clk < = 24 'd0 ;
end
else if ( cnt_clk = = MAX - 1 'd1 ) begin
cnt_clk < = 24 'd0 ;
end
else begin
cnt_clk < = cnt_clk + 1 'd1 ;
end
end
always @ ( posedge clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
led < = 1 'b0 ;
end
else if ( cnt_clk = = MAX - 1 'd1 ) begin
led < = ~ led ;
end
else begin
led < = led ;
end
end
endmodule