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//这个分频里面全是使用全局时钟树，无论高速还是低速系统都更稳定
module divider_six1 (
input wire sys_clk ,
input wire sys_rst_n ,
output reg led
) ;
parameter MAX = 23 'd8 _333_333 ;
reg [ 2 : 0 ] cnt ;
reg flag ;
reg [ 22 : 0 ] cnt_flag ;
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
cnt < = 3 'd0 ;
end
else if ( cnt = = 3 'd5 ) begin
cnt < = 3 'd0 ;
end
else begin
cnt < = cnt + 1 'd1 ;
end
end
//使用flag计数0~5，
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
flag < = 1 'b0 ;
end
else if ( cnt = = 3 'd5 ) begin
flag < = 1 'b1 ;
end
else begin
flag < = 1 'b0 ;
end
end
//根据脉冲信号加1
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
cnt_flag < = 23 'd0 ;
end
else if ( cnt_flag = = MAX - 1 'd1 ) begin
cnt_flag < = 23 'd0 ;
end
else if ( flag ) begin
cnt_flag < = cnt_flag + 1 'd1 ;
end
else begin
cnt_flag < = cnt_flag ;
end
end
always @ ( posedge sys_clk or negedge sys_rst_n ) begin
if ( ! sys_rst_n ) begin
led < = 1 'b0 ;
end
else if ( cnt_flag = = MAX - 1 'd1 ) begin
led < = ~ led ;
end
else begin
led < = led ;
end
end
endmodule