commit ef1d14610d5bdd816eff181344577c01a56fbd06 Author: lincaigui <18166451309@163.com> Date: Tue Apr 23 13:23:58 2024 +0800 finish diff --git a/doc/infinite_state_machine.png b/doc/infinite_state_machine.png new file mode 100644 index 0000000..e2ebc30 Binary files /dev/null and b/doc/infinite_state_machine.png differ diff --git a/doc/simulation.png b/doc/simulation.png new file mode 100644 index 0000000..fd72c7c Binary files /dev/null and b/doc/simulation.png differ diff --git a/doc/时序图.vsdx b/doc/时序图.vsdx new file mode 100644 index 0000000..69f8c0f Binary files /dev/null and b/doc/时序图.vsdx differ diff --git a/doc/模块图.vsdx b/doc/模块图.vsdx new file mode 100644 index 0000000..9abb28c Binary files /dev/null and b/doc/模块图.vsdx differ diff --git a/doc/状态机图.vsdx b/doc/状态机图.vsdx new file mode 100644 index 0000000..5a2c015 Binary files /dev/null and b/doc/状态机图.vsdx differ diff --git a/rtl/traffic_light.v b/rtl/traffic_light.v new file mode 100644 index 0000000..7aca11b --- /dev/null +++ b/rtl/traffic_light.v @@ -0,0 +1,121 @@ +module traffic_light( + input wire sys_clk , + input wire sys_rst_n , + + output reg [3: 0] led +); +parameter MAX_S = 26'd50_000_000;//1s +parameter MAX_83 = 7'd83;//83s +//状态空间,自然数编码 +parameter IDLE = 2'd0, + RED = 2'd1, + GREEN = 2'd2, + YELLOW = 2'd3; +//动作空间 +parameter ACT1 = 4'b0000, + ACT2 = 4'b0100, + ACT3 = 4'b0010, + ACT4 = 4'b0001; + +reg [1: 0] c_state;//现态，current state +reg [1: 0] n_state;//次态，next state + +reg [25: 0] cnt_s;//1s计数寄存器 +reg [6: 0] cnt_83;//83s计数寄存器 +wire start;//进入红绿灯场景标志 +assign start = 1'b1; +//约束cnt_s +always @(posedge sys_clk or negedge sys_rst_n) begin + if(!sys_rst_n)begin + cnt_s <= 26'd0; + end + else if(cnt_s == MAX_S - 1'd1)begin + cnt_s <= 26'd0; + end + else begin + cnt_s <= cnt_s + 1'd1; + end +end + +//约束cnt_83 +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + cnt_83 <= 7'd0; + end + //计到83-1，并且计1s + else if((cnt_83 == MAX_83 - 1'd1) && (cnt_s == MAX_S - 1'd1))begin + cnt_83 <= 7'd0; + end + //每计1s加1 + else if(cnt_s == MAX_S - 1'd1)begin + cnt_83 <=cnt_83 + 1'd1; + end + //其他时刻保持 + else begin + cnt_83 <= cnt_83; + end +end + +//三段式有限状态机，第一段，时序逻辑 +always @(posedge sys_clk or negedge sys_rst_n)begin + if(!sys_rst_n)begin + c_state <= IDLE;//初始化当前状态为IDLE + end + else begin + c_state <= n_state;//其他时钟上升沿，次态赋给现态 + end +end +//第二段，组合逻辑，描述状态跳转关系 +always @(*)begin + case(c_state) + IDLE : begin + if(start == 1'b1)begin//条件 + n_state = RED;//跳转至下一个状态 + end + else begin + n_state = IDLE;//保持当前状态 + end + end + RED : begin + if((cnt_83 == 7'd59) && (cnt_s == MAX_S - 1'd1))begin + n_state = GREEN; + end + else begin + n_state = RED; + end + + end + GREEN : begin + if((cnt_83 == 7'd79) && (cnt_s == MAX_S - 1'd1))begin + n_state = YELLOW; + end + else begin + n_state = GREEN; + end + end + YELLOW : begin + if((cnt_83 == MAX_83 - 1'd1) && (cnt_s == MAX_S - 1'd1))begin + n_state = RED; + end + else begin + n_state = YELLOW; + end + end + default : begin + n_state = IDLE; + end + endcase +end +//第三段，可以组合也可以时序 +always@(*)begin + case(c_state) + IDLE : led = ACT1; + RED : led = ACT2; + GREEN : led = ACT3; + YELLOW : led = ACT4; + default : led = ACT1; + endcase +end + + +endmodule \ No newline at end of file diff --git a/tb/traffic_light_tb.v b/tb/traffic_light_tb.v new file mode 100644 index 0000000..39171de --- /dev/null +++ b/tb/traffic_light_tb.v @@ -0,0 +1,25 @@ +`timescale 1ns/1ns +module traffic_light_tb(); +parameter CYCLE = 20; +reg sys_clk ; +reg sys_rst_n ; +wire [3: 0] led ; +always #(CYCLE / 2) sys_clk = ~sys_clk; +initial begin + sys_clk = 1'b0; + sys_rst_n = 1'b0; + #(CYCLE); + sys_rst_n = 1'b1; + #(CYCLE * 5 * 83);//20 x 5 x 83 = 8300ns + $stop; +end + +traffic_light traffic_light_inst( +.sys_clk (sys_clk) , +.sys_rst_n (sys_rst_n) , + +.led (led) +); + +defparam traffic_light_inst.MAX_S = 5;//1s-->5 x 20 = 100ns +endmodule \ No newline at end of file diff --git a/tcl/traffic_light.tcl b/tcl/traffic_light.tcl new file mode 100644 index 0000000..e79999f --- /dev/null +++ b/tcl/traffic_light.tcl @@ -0,0 +1,26 @@ +# Copyright (C) 2018 Intel Corporation. All rights reserved. +# Your use of Intel Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Intel Program License +# Subscription Agreement, the Intel Quartus Prime License Agreement, +# the Intel FPGA IP License Agreement, or other applicable license +# agreement, including, without limitation, that your use is for +# the sole purpose of programming logic devices manufactured by +# Intel and sold by Intel or its authorized distributors. Please +# refer to the applicable agreement for further details. + +# Quartus Prime Version 18.1.0 Build 625 09/12/2018 SJ Standard Edition +# File: D:\sdkj_projects\led_flow_3\tcl\led_flow_3.tcl +# Generated on: Tue Dec 26 15:16:28 2023 + +package require ::quartus::project + +set_location_assignment PIN_G15 -to led[0] +set_location_assignment PIN_F16 -to led[1] +set_location_assignment PIN_F15 -to led[2] +set_location_assignment PIN_D16 -to led[3] +set_location_assignment PIN_E1 -to sys_clk +set_location_assignment PIN_E15 -to sys_rst_n