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25 lines
552 B
Verilog
25 lines
552 B
Verilog
`timescale 1ns/1ns
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module traffic_light_tb();
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parameter CYCLE = 20;
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reg sys_clk ;
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reg sys_rst_n ;
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wire [3: 0] led ;
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always #(CYCLE / 2) sys_clk = ~sys_clk;
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initial begin
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sys_clk = 1'b0;
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sys_rst_n = 1'b0;
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#(CYCLE);
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sys_rst_n = 1'b1;
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#(CYCLE * 5 * 83);//20 x 5 x 83 = 8300ns
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$stop;
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end
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traffic_light traffic_light_inst(
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.led (led)
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);
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defparam traffic_light_inst.MAX_S = 5;//1s-->5 x 20 = 100ns
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endmodule |