full_adder/rtl/full_adder.v

module full_adder(
    input   wire            sys_clk     ,
    input   wire            sys_rst_n   ,
    input   wire  [2: 0]    key_in      ,//in1, in2, cin

    output  wire            cout        ,
    output  wire            sum
);
wire [2: 0] key_out;
wire sum0, cout0, cout1;
reg flag_key0;
reg flag_key1;
reg flag_key2;

always @(posedge sys_clk or negedge sys_rst_n)begin
    if(!sys_rst_n)begin
        flag_key0 <= 1'b0;
        flag_key1 <= 1'b0;
        flag_key2 <= 1'b0;
    end 
    else if(key_out[0])begin
        flag_key0 <= ~flag_key0;
        flag_key1 <= flag_key1;
        flag_key2 <= flag_key2;
    end 
    else if(key_out[1])begin
        flag_key0 <= flag_key0;
        flag_key1 <= ~flag_key1;
        flag_key2 <= flag_key2;
    end 
    else if(key_out[2])begin
        flag_key0 <= flag_key0;
        flag_key1 <= flag_key1;
        flag_key2 <= ~flag_key2;
    end 
    else begin
        flag_key0 <= flag_key0;
        flag_key1 <= flag_key1;
        flag_key2 <= flag_key2;
    end 
end 
half_adder half_adder0(
.cin      ({flag_key0, flag_key1}),//in1, in2

.sum      (sum0),
.cout     (cout0) 
);
half_adder half_adder1(
.cin      ({sum0, flag_key2}),//in1, in2

.sum      (sum),
.cout     (cout1) 
);

key_filter #(.KEY_W(3), .DELAY(1000_000)) key_filter_inst(//2
.sys_clk        (sys_clk) ,
.sys_rst_n      (sys_rst_n) ,
.key_in         (key_in),
.key_out        (key_out)
);	    

assign cout = cout0 | cout1;
endmodule