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63 lines
1.4 KiB
Verilog
63 lines
1.4 KiB
Verilog
module full_adder(
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input wire sys_clk ,
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input wire sys_rst_n ,
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input wire [2: 0] key_in ,//in1, in2, cin
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output wire cout ,
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output wire sum
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);
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wire [2: 0] key_out;
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wire sum0, cout0, cout1;
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reg flag_key0;
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reg flag_key1;
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reg flag_key2;
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always @(posedge sys_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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flag_key0 <= 1'b0;
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flag_key1 <= 1'b0;
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flag_key2 <= 1'b0;
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end
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else if(key_out[0])begin
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flag_key0 <= ~flag_key0;
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flag_key1 <= flag_key1;
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flag_key2 <= flag_key2;
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end
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else if(key_out[1])begin
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flag_key0 <= flag_key0;
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flag_key1 <= ~flag_key1;
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flag_key2 <= flag_key2;
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end
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else if(key_out[2])begin
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flag_key0 <= flag_key0;
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flag_key1 <= flag_key1;
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flag_key2 <= ~flag_key2;
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end
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else begin
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flag_key0 <= flag_key0;
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flag_key1 <= flag_key1;
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flag_key2 <= flag_key2;
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end
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end
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half_adder half_adder0(
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.cin ({flag_key0, flag_key1}),//in1, in2
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.sum (sum0),
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.cout (cout0)
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);
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half_adder half_adder1(
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.cin ({sum0, flag_key2}),//in1, in2
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.sum (sum),
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.cout (cout1)
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);
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key_filter #(.KEY_W(3), .DELAY(1000_000)) key_filter_inst(//2
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.sys_clk (sys_clk) ,
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.sys_rst_n (sys_rst_n) ,
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.key_in (key_in),
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.key_out (key_out)
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);
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assign cout = cout0 | cout1;
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endmodule |