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85 lines
1.8 KiB
Coq

7 months ago
module uart_top(
input wire sys_clk ,
input wire sys_rst_n ,
input wire rx ,
output wire tx ,
output wire led_ready
);
wire [7: 0] data_byte ;
wire [7: 0] data_out ;
wire ready ;
wire comm_finish ;
wire tx_vld ;
wire rx_vld ;
reg rcv_start ;
always @(posedge sys_clk or negedge sys_rst_n)begin
if(!sys_rst_n)begin
rcv_start <= 1'b1;
end
else if(ready)begin
rcv_start <= 1'b0;
end
else if(comm_finish)begin
rcv_start <= 1'b1;
end
else begin
rcv_start <= rcv_start;
end
end
uart_rx uart_rx_inst(
.sys_clk (sys_clk) ,
.sys_rst_n (sys_rst_n) ,
.rx_din (rx) ,//
.rcv_start (rcv_start) ,
.rx_dout (data_byte) ,//
.rx_vld (rx_vld) //
);
uart_tx uart_tx_inst(
.sys_clk (sys_clk) ,
.sys_rst_n (sys_rst_n) ,
.tx_din (data_out) ,//
.rx_vld (rx_vld) ,//
.tx_vld (tx_vld) ,
.tx_dout (tx)//
);
device_ready device_ready_inst(
.sys_clk (sys_clk) ,
.sys_rst_n (sys_rst_n) ,
.data_in (data_byte) ,
.rx_vld (rx_vld) ,
.ready (ready)
);
command_send command_send_inst(
.sys_clk (sys_clk) ,
.sys_rst_n (sys_rst_n) ,
.tx_vld (tx_vld) ,
.comm_finish (comm_finish),
.data_out (data_out)
);
led_driver led_driver_inst(
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n),
.rx_data (data_byte),
.led_ready (led_ready)
);
endmodule