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lincaigui 7 months ago
parent de5054a911
commit 97cbfb3f2b
7 changed files with 60 additions and 7 deletions
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rtl/i2c_ctrl.v
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@ -33,6 +33,7 @@ reg i2c_clk;
reg [9: 0] cnt_wait ;//1000us reg [9: 0] cnt_wait ;//1000us
reg skip_en_1 ;//步骤1跳转信号 reg skip_en_1 ;//步骤1跳转信号
reg skip_en_2 ;//步骤2跳转信号 reg skip_en_2 ;//步骤2跳转信号
reg skip_en_3 ;//步骤3跳转信号
reg [2: 0] step ;//步骤 reg [2: 0] step ;//步骤
reg [1: 0] cnt_i2c_clk ;//i2c计数器 reg [1: 0] cnt_i2c_clk ;//i2c计数器
reg [2: 0] cnt_bit ;//bit计数器 reg [2: 0] cnt_bit ;//bit计数器
@ -86,13 +87,13 @@ end
//状态机第二段 //状态机第二段
always @(*)begin always @(*)begin
case(state_c) case(state_c)
IDLE: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1))begin IDLE: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = START; state_n = START;
end end
else begin else begin
state_n = IDLE; state_n = IDLE;
end end
START: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1))begin START: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = SLAVE_ADDR; state_n = SLAVE_ADDR;
end end
else begin else begin
@ -101,19 +102,19 @@ always @(*)begin
SLAVE_ADDR: if(skip_en_1 == 1'b1)begin SLAVE_ADDR: if(skip_en_1 == 1'b1)begin
state_n = WAIT; state_n = WAIT;
end end
else if(skip_en_2 == 1'b1)begin else if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = ACK_1; state_n = ACK_1;
end end
else begin else begin
state_n = SLAVE_ADDR; state_n = SLAVE_ADDR;
end end
ACK_1: if(skip_en_2 == 1'b1)begin ACK_1: if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = DEVICE_ADDR; state_n = DEVICE_ADDR;
end end
else begin else begin
state_n = ACK_1; state_n = ACK_1;
end end
DEVICE_ADDR:if(skip_en_2 == 1'b1)begin DEVICE_ADDR:if((skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = ACK_2; state_n = ACK_2;
end end
else begin else begin
@ -122,6 +123,9 @@ always @(*)begin
ACK_2: if(skip_en_2 == 1'b1)begin ACK_2: if(skip_en_2 == 1'b1)begin
state_n = DATA; state_n = DATA;
end end
else if(skip_en_3 == 1'b1)begin
state_n = STOP;
end
else begin else begin
state_n = ACK_2; state_n = ACK_2;
end end
@ -143,7 +147,7 @@ always @(*)begin
else begin else begin
state_n = WAIT; state_n = WAIT;
end end
STOP: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1))begin STOP: if((skip_en_1 == 1'b1) || (skip_en_2 == 1'b1) || (skip_en_3 == 1'b1))begin
state_n = IDLE; state_n = IDLE;
end end
else begin else begin
@ -158,8 +162,9 @@ end
always @(posedge i2c_clk or negedge sys_rst_n)begin always @(posedge i2c_clk or negedge sys_rst_n)begin
if(!sys_rst_n)begin if(!sys_rst_n)begin
cnt_wait <= 10'd0; cnt_wait <= 10'd0;
skip_en_1 <= 1'b0; skip_en_1 <= 1'b0;//步骤1跳转信号
skip_en_2 <= 1'b0;//步骤2跳转信号 skip_en_2 <= 1'b0;//步骤2跳转信号
skip_en_3 <= 1'b0;//步骤3跳转信号
step <= 3'd0; step <= 3'd0;
cnt_i2c_clk <= 2'd0; cnt_i2c_clk <= 2'd0;
cnt_bit <= 3'd0; cnt_bit <= 3'd0;
@ -186,6 +191,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((cnt_wait == MAX - 2'd2) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
end end
START: begin START: begin
cnt_i2c_clk <= cnt_i2c_clk + 1'd1; cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
@ -201,6 +212,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
end end
SLAVE_ADDR: begin SLAVE_ADDR: begin
cnt_i2c_clk <= cnt_i2c_clk + 1'd1; cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
@ -216,6 +233,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((cnt_i2c_clk == 2'd2) && (step == 3'd2) && (cnt_bit == 3'd7))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin
cnt_bit <= 3'd0; cnt_bit <= 3'd0;
end end
@ -234,6 +257,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
end end
DEVICE_ADDR:begin DEVICE_ADDR:begin
cnt_i2c_clk <= cnt_i2c_clk + 1'b1; cnt_i2c_clk <= cnt_i2c_clk + 1'b1;
@ -252,6 +281,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
end end
ACK_2: begin ACK_2: begin
cnt_i2c_clk <= cnt_i2c_clk + 1; cnt_i2c_clk <= cnt_i2c_clk + 1;
@ -261,6 +296,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((ack == 1'b1) && (cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
end end
DATA: begin DATA: begin
cnt_i2c_clk <= cnt_i2c_clk + 1'b1; cnt_i2c_clk <= cnt_i2c_clk + 1'b1;
@ -317,6 +358,12 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
else begin else begin
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
end end
if((cnt_i2c_clk == 2'd2) && (step == 3'd2))begin
skip_en_3 <= 1'b1;
end
else begin
skip_en_3 <= 1'b0;
end
if(cnt_i2c_clk == 2'd2)begin if(cnt_i2c_clk == 2'd2)begin
i2c_end <= 1'b1; i2c_end <= 1'b1;
end end
@ -334,6 +381,7 @@ always @(posedge i2c_clk or negedge sys_rst_n)begin
cnt_wait <= 10'd0; cnt_wait <= 10'd0;
skip_en_1 <= 1'b0; skip_en_1 <= 1'b0;
skip_en_2 <= 1'b0; skip_en_2 <= 1'b0;
skip_en_3 <= 1'b0;
step <= step; step <= step;
cnt_i2c_clk <= 2'd0; cnt_i2c_clk <= 2'd0;
cnt_bit <= 3'd0; cnt_bit <= 3'd0;
@ -362,6 +410,11 @@ always @(*)begin
device_addr= {8'hef}; device_addr= {8'hef};
wr_data = {8'h00}; wr_data = {8'h00};
end end
3'd2: begin
slave_addr = {SLAVE_ID, 1'b0};
device_addr= {8'hef};
wr_data = {8'h00};
end
default:begin default:begin
slave_addr = 8'h0; slave_addr = 8'h0;
device_addr = 8'h0; device_addr = 8'h0;

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