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module i2c_ctrl(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire scl ,
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inout wire sda
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);
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parameter I2C_CLK_DIV = 5'd24,
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MAX = 10'd1000,
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SLAVE_ID = 7'h73;
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//状态机参数定义
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parameter IDLE = 3'd0,
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START = 3'd1,
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SLAVE_ADDR= 3'd2,
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WAIT = 3'd3,
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STOP = 3'd4;
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reg [2: 0] state_c;
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reg [2: 0] state_n;
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////
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//i2c时钟计数器
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reg [4: 0] cnt_clk;
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reg i2c_clk;
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/////
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//中间信号定义
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reg [9: 0] cnt_wait ;//1000us
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reg skip_en_1 ;//跳转信号
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reg [2: 0] step ;//步骤
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reg [1: 0] cnt_i2c_clk ;//
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reg [2: 0] cnt_bit ;//bit计数器
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reg i2c_end ;//i2c结束信号
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wire sda_en ;
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wire sda_in ;
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reg i2c_sda ;
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reg i2c_scl ;
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reg [7: 0] slave_addr ;
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reg [7: 0] device_addr ;
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reg [7: 0] wr_data ;
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//三态门
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assign sda_en = 1'b1;//主机控制从机
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assign sda_in = sda;
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assign sda = (sda_en == 1'b1)? i2c_sda : 1'bz;
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//i2c驱动时钟设计
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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cnt_clk <= 5'd0;
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end
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else if(cnt_clk == I2C_CLK_DIV)begin
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cnt_clk <= 5'd0;
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end
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else begin
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cnt_clk <= cnt_clk + 1;
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end
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end
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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i2c_clk <= 1'b1;
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end
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else if(cnt_clk == I2C_CLK_DIV)begin
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i2c_clk <= ~i2c_clk;
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end
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else begin
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i2c_clk <= i2c_clk;
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end
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end
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/////////
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//状态机，第一段
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always @(posedge sys_clk or negedge sys_rst_n) begin
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if(!sys_rst_n)begin
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state_c <= IDLE;
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end
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else begin
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state_c <= state_n;
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end
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end
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//状态机第二段
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always @(*)begin
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case(state_c)
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IDLE: if(skip_en_1 == 1'b1)begin
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state_n = START;
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end
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else begin
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state_n = IDLE;
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end
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START: if(skip_en_1 == 1'b1)begin
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state_n = SLAVE_ADDR;
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end
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else begin
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state_n = START;
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end
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SLAVE_ADDR: if(skip_en_1 == 1'b1)begin
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state_n = WAIT;
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end
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else begin
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state_n = SLAVE_ADDR;
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end
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WAIT: if(skip_en_1 == 1'b1)begin
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state_n = STOP;
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end
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else begin
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state_n = WAIT;
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end
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STOP: if(skip_en_1 == 1'b1)begin
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state_n = IDLE;
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end
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else begin
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state_n = STOP;
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end
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default: begin
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state_n = IDLE;
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end
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endcase
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end
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//状态机第三段
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always @(posedge i2c_clk or negedge sys_rst_n)begin
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if(!sys_rst_n)begin
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cnt_wait <= 10'd0;
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skip_en_1 <= 1'b0;
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step <= 3'd0;
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cnt_i2c_clk <= 2'd0;
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cnt_bit <= 3'd0;
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i2c_end <= 1'b0;
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end
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else begin
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case(state_c)
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IDLE: begin
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if(cnt_wait == MAX - 1)begin
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cnt_wait <= 10'd0;
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end
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else begin
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cnt_wait <= cnt_wait + 1;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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end
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START: begin
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cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
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if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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end
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SLAVE_ADDR: begin
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cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
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if((cnt_i2c_clk == 2'd2) && (cnt_bit == 3'd7) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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if((cnt_bit == 3'd7) && (cnt_i2c_clk == 2'd3))begin
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cnt_bit <= 3'd0;
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end
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else if(cnt_i2c_clk == 2'd3)begin
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cnt_bit <= cnt_bit + 1'd1;
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end
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else begin
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cnt_bit <= cnt_bit;
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end
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end
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WAIT: begin
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if(cnt_wait == MAX - 1'd1)begin
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cnt_wait = 10'd0;
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end
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else begin
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cnt_wait <= cnt_wait + 1'd1;
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end
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if((cnt_wait == MAX - 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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end
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STOP: begin
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cnt_i2c_clk <= cnt_i2c_clk + 1'd1;
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if((cnt_i2c_clk == 2'd2) && (step == 3'd0))begin
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skip_en_1 <= 1'b1;
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end
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else begin
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skip_en_1 <= 1'b0;
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end
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if(cnt_i2c_clk == 2'd2)begin
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i2c_end <= 1'b1;
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end
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else begin
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i2c_end <= 1'b0;
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end
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if(i2c_end == 1'b1)begin
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step <= step + 1'd1;
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end
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else begin
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step <= step;
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end
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end
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default: begin
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cnt_wait <= 10'd0;
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skip_en_1 <= 1'b0;
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step <= step;
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cnt_i2c_clk <= 2'd0;
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cnt_bit <= 3'd0;
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i2c_end <= 1'b0;
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end
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endcase
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end
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end
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//step
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always @(*)begin
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case(step)
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3'd0: begin
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slave_addr = {SLAVE_ID, 1'b0};
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device_addr = 8'h0;
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wr_data = 8'h0;
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end
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default:begin
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slave_addr = 8'h0;
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device_addr = 8'h0;
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wr_data = 8'h0;
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end
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endcase
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end
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//i2c_scl
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always @(*)begin
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case(state_c)
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IDLE: i2c_scl = 1'b1;
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START: i2c_scl = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0;
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SLAVE_ADDR: i2c_scl = ((cnt_i2c_clk == 2'd1) || (cnt_i2c_clk == 2'd2)) ? 1'b1 : 1'b0;
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WAIT: i2c_scl = 1'b0;
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STOP: i2c_scl = (cnt_i2c_clk >= 2'd1) ? 1'b1 : 1'b0;
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endcase
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end
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//i2c_sda
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always @(*)begin
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case(state_c)
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IDLE: i2c_sda = 1'b1;
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START: i2c_sda = (cnt_i2c_clk >= 2'd1) ? 1'b0 : 1'b1;
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SLAVE_ADDR: i2c_sda = slave_addr[7 - cnt_bit];
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WAIT: i2c_sda = 1'b0;
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STOP: i2c_sda = (cnt_i2c_clk >= 2'd2) ? 1'b1 : 1'b0;
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default: i2c_sda = 1'b1;
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endcase
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end
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assign scl = i2c_scl;
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endmodule |