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40 lines
962 B
Verilog
40 lines
962 B
Verilog
module ges_recognize(
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input wire sys_clk ,
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input wire sys_rst_n ,
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output wire scl ,
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inout wire sda
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);
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wire [2: 0] step ;
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wire [5: 0] cfg_num ;
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wire [15: 0] cfg_data ;
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wire cfg_start ;
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wire i2c_clk ;
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wire i2c_start ;
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paj7620_cfg paj7620_cfg_inst(
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.i2c_clk (i2c_clk ),
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.sys_rst_n (sys_rst_n ),
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.cfg_start (cfg_start ),
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.step (step ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.i2c_start (i2c_start )
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);
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i2c_ctrl i2c_ctrl_inst(
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.sys_clk (sys_clk ),
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.sys_rst_n (sys_rst_n ),
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.i2c_start (i2c_start ),
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.cfg_num (cfg_num ),
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.cfg_data (cfg_data ),
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.cfg_start (cfg_start ),
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.step (step ),
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.i2c_clk (i2c_clk ),
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.scl (scl ),
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.sda (sda )
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);
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endmodule |