You cannot select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
64 lines
1.7 KiB
Verilog
64 lines
1.7 KiB
Verilog
module ges_recognize(
|
|
input wire sys_clk ,
|
|
input wire sys_rst_n ,
|
|
|
|
output wire scl ,
|
|
inout wire sda ,
|
|
output wire [3: 0] led ,
|
|
output wire tx
|
|
);
|
|
wire [2: 0] step ;
|
|
wire [5: 0] cfg_num ;
|
|
wire [15: 0] cfg_data ;
|
|
wire cfg_start ;
|
|
wire i2c_clk ;
|
|
wire i2c_start ;
|
|
wire [7: 0] po_data ;
|
|
wire tx_vld ;
|
|
reg send_flag ;
|
|
wire rx_vld ;
|
|
|
|
assign rx_vld = po_data != 8'h00;
|
|
paj7620_cfg paj7620_cfg_inst(
|
|
.i2c_clk (i2c_clk ),
|
|
.sys_rst_n (sys_rst_n ),
|
|
.cfg_start (cfg_start ),
|
|
.step (step ),
|
|
|
|
.cfg_num (cfg_num ),
|
|
.cfg_data (cfg_data ),
|
|
.i2c_start (i2c_start )
|
|
);
|
|
i2c_ctrl i2c_ctrl_inst(
|
|
.sys_clk (sys_clk ),
|
|
.sys_rst_n (sys_rst_n ),
|
|
.i2c_start (i2c_start ),
|
|
.cfg_num (cfg_num ),
|
|
.cfg_data (cfg_data ),
|
|
|
|
.cfg_start (cfg_start ),
|
|
.step (step ),
|
|
.i2c_clk (i2c_clk ),
|
|
.scl (scl ),
|
|
.sda (sda ),
|
|
.po_data (po_data )
|
|
|
|
);
|
|
uart_tx uart_tx_inst(
|
|
.sys_clk (sys_clk),
|
|
.sys_rst_n (sys_rst_n),
|
|
.tx_din (po_data),//并行输入，接受模块传入
|
|
.rx_vld (rx_vld),//接受模块，串转并有效信号
|
|
|
|
|
|
.tx_vld (tx_vld),
|
|
.tx_dout (tx)//串行输出
|
|
);
|
|
led_ctrl led_ctrl_inst(
|
|
.sys_clk (sys_clk ),
|
|
.sys_rst_n (sys_rst_n ),
|
|
.po_data (po_data ),
|
|
|
|
.led (led )
|
|
);
|
|
endmodule |